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user-1042
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Registered: ‎02-18-2021

10G Example Design Upgrade to 2020.1

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Currently working on an effort to upgrade the 10G Example Design (https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet) to 2020.1

Has anyone done this successfully? Could they possibly share their steps taken?

What I've done is upgrade the HDL to 2020.2 (upgrade IP, regenerate bitsream). Then use petalinux-create with the zynqMP template. And manually add changes in configs, meta-user. Ran petalinux-config, petalinux-build, and petalinux-package with the new bit file.

I'm running into this error while booting

[ 5.251455] xilinx_axienet 80010000.ethernet: IRQ index 0 not found
[ 5.257721] xilinx_axienet 80010000.ethernet: Ethernet core IRQ not defined
[ 5.264684] xilinx_axienet 80010000.ethernet: couldn't find phy i/f

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claytonr
Xilinx Employee
Xilinx Employee
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Registered: ‎08-15-2018

Hey @user-1042,

My name is Clayton and I maintain the ZCU102-Ethernet repo in my spare time.

 

I was able to build the design in 2020.1 a little while ago - I've opened it back up and running here in my test bench as I write this (on eth1):

claytonr_0-1617061750874.png

 

I seem to recall having to mess around with the system-user.dtsi file to get everything to work properly after the upgrade from 2019.2 to 2020.1 since the labels for the si570 had changed.

 

Here's my system-user.dtsi file:

 

 

/include/ "system-conf.dtsi"
/ {
};

&i2c1 {
    status = "okay";
    clock-frequency = <400000>;
    i2c-mux@74 { /* u34 */
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x74>;
        i2c@3 { /* i2c mw 74 0 8 */
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
            si570_2: clock-generator@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <156250000>;
            };
        };
    };
};

 

 

 

If you don't have the right clock generator entry in the DT, the ZCU102 template device tree (make sure in your new project you've set the DTG machine template name to "zcu102-rev1.0") will automatically program that clock to 148.5MHz I believe to support HDMI, which makes the 10G IP unhappy.

 

Barring that, if you PM me I can send you this design I have here - although I'd prefer to fix it out in the open on the forum here in case anyone else runs in to the same problem.

 

Hope this helps!

 

Thanks,

Clayton

Edit: Also don't worry about the "couldn't find phy i/f" message, that's to be expected since the 10G IP doesn't have an MDIO interface to tie in to the rest of the phydev framework. Here you can see the message on my working project:

claytonr_1-1617062116552.png

 

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claytonr
Xilinx Employee
Xilinx Employee
810 Views
Registered: ‎08-15-2018

Hey @user-1042,

My name is Clayton and I maintain the ZCU102-Ethernet repo in my spare time.

 

I was able to build the design in 2020.1 a little while ago - I've opened it back up and running here in my test bench as I write this (on eth1):

claytonr_0-1617061750874.png

 

I seem to recall having to mess around with the system-user.dtsi file to get everything to work properly after the upgrade from 2019.2 to 2020.1 since the labels for the si570 had changed.

 

Here's my system-user.dtsi file:

 

 

/include/ "system-conf.dtsi"
/ {
};

&i2c1 {
    status = "okay";
    clock-frequency = <400000>;
    i2c-mux@74 { /* u34 */
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x74>;
        i2c@3 { /* i2c mw 74 0 8 */
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
            si570_2: clock-generator@5d {
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>;
                factory-fout = <156250000>;
                clock-frequency = <156250000>;
            };
        };
    };
};

 

 

 

If you don't have the right clock generator entry in the DT, the ZCU102 template device tree (make sure in your new project you've set the DTG machine template name to "zcu102-rev1.0") will automatically program that clock to 148.5MHz I believe to support HDMI, which makes the 10G IP unhappy.

 

Barring that, if you PM me I can send you this design I have here - although I'd prefer to fix it out in the open on the forum here in case anyone else runs in to the same problem.

 

Hope this helps!

 

Thanks,

Clayton

Edit: Also don't worry about the "couldn't find phy i/f" message, that's to be expected since the 10G IP doesn't have an MDIO interface to tie in to the rest of the phydev framework. Here you can see the message on my working project:

claytonr_1-1617062116552.png

 

View solution in original post

user-1042
Visitor
Visitor
795 Views
Registered: ‎02-18-2021

Do you remember if you created a new petalinux project? Or just upgraded the 2019.2 one? If you did the latter, how did you do that? Did you generate a BSP first and then use petalinux-create -s *.bsp

I'll give it one more try and then probably PM you for your design

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claytonr
Xilinx Employee
Xilinx Employee
754 Views
Registered: ‎08-15-2018

Hey @user-1042,
I created a new PetaLinux project - I actually didn't copy anything over from the old one since there aren't too many things that need to be updated, just the rootfs packages that you'd like to use (I usually include phytool, ethtool, and iperf3), and the system-user.dtsi file, although that will have to be modified like I described above.

 

Thanks,

Clayton

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tkolcak
Observer
Observer
522 Views
Registered: ‎09-21-2018

Hi Clayton,

When I modify the device tree as you suggested, I get error when compiling device tree for 2020.1.

ERROR (duplicate_label): /amba/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator3@5d: Duplicate label 'si570_2' on /amba/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator3@5d and /amba/i2c@ff030000/i2c-mux@74/i2c@3/clock-generator@5d
ERROR: Input tree has errors, aborting (use -f to force output)

Do you have any idea on the source of the error ?

Thanks

 

 

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claytonr
Xilinx Employee
Xilinx Employee
509 Views
Registered: ‎08-15-2018

Hi @tkolcak,

The error is pretty subtle, since it's buried in such a long string, but essentially it looks like your clock generator label didn't get updated when you modified system-user.dtsi.

 

In 2020.1 they removed the "3" from

clock-generator3@5d

and instead the node became:

clock-generator@5d

 

You see the duplicate label error because this creates a new node rather than modifying the existing node, and also assigns it the label si570_2.

 

To resolve it, just double check your system-user.dtsi file and make sure you're using 

clock-generator@5d

 

Hope this helps!

 

Thanks,

Clayton

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tkolcak
Observer
Observer
501 Views
Registered: ‎09-21-2018

Hi Clayton,

Many thanks for the quick response. I modified the device tree as you suggested and I don't see any compilation or build errors. Kudos !

However, I couldn't get the 10GBit link up. I shared below corresponding boot messages for eth1:

[ 5.336740] xilinx_axienet 80010000.ethernet: IRQ index 0 not found
[ 5.343002] xilinx_axienet 80010000.ethernet: Ethernet core IRQ not defined
[ 5.349959] xilinx_axienet 80010000.ethernet: couldn't find phy i/f
[ 16.137988] xilinx_axienet 80010000.ethernet eth1: __axienet_device_reset: DMA reset timeout!
[ 16.147925] xilinx_axienet 80010000.ethernet eth1: __axienet_device_reset: DMA reset timeout!
[ 16.158783] xilinx_axienet 80010000.ethernet eth1: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration

Do you have any ideas on these warnings/errors ?

Thanks

 

 

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tkolcak
Observer
Observer
391 Views
Registered: ‎09-21-2018

@claytonr and all interested in this topic,

After a clean build (mrproper) of my project, I dont get DMA reset timeout warnings in the boot messages. However, I still get the following messages :

[ 5.336740] xilinx_axienet 80010000.ethernet: IRQ index 0 not found
[ 5.343002] xilinx_axienet 80010000.ethernet: Ethernet core IRQ not defined
[ 5.349959] xilinx_axienet 80010000.ethernet: couldn't find phy i/f

When I check autogenerated pl.dtsi, I don't see any interrupt node for ethernet device. This is also inconsistent with the device tree in Linux AXI Ethernet driver - Xilinx Wiki - Confluence (atlassian.net)

Do you have any idea on the missing interrupt node ?

Auto-generated pl.dtsi ethernet node

xxv_ethernet_0: ethernet@80010000 {
axistream-connected = <&axi_dma_0>;
axistream-control-connected = <&axi_dma_0>;
clock-frequency = <100000000>;
clock-names = "rx_core_clk_0", "dclk", "s_axi_aclk_0";
clocks = <&misc_clk_0>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
compatible = "xlnx,xxv-ethernet-3.2", "xlnx,xxv-ethernet-1.0";
device_type = "network";
local-mac-address = [00 0a 35 00 00 01];
phy-mode = "base-r";
reg = <0x0 0x80010000 0x0 0x10000>;
xlnx = <0x0>;
xlnx,add-gt-cntrl-sts-ports = <0x0>;
xlnx,anlt-clk-in-mhz = <0x64>;
xlnx,axis-tdata-width = <0x40>;
xlnx,axis-tkeep-width = <0x7>;
xlnx,base-r-kr = "BASE-R";
xlnx,clocking = "Asynchronous";
xlnx,cmac-core-select = "CMACE4_X0Y0";
xlnx,core = "Ethernet MAC+PCS/PMA 64-bit";
xlnx,data-path-interface = "AXI Stream";
xlnx,enable-datapath-parity = <0x0>;
xlnx,enable-pipeline-reg = <0x0>;
xlnx,enable-preemption = <0x0>;
xlnx,enable-preemption-fifo = <0x0>;
xlnx,enable-rx-flow-control-logic = <0x0>;
xlnx,enable-time-stamping = <0x0>;
xlnx,enable-tx-flow-control-logic = <0x0>;
xlnx,enable-vlane-adjust-mode = <0x0>;
xlnx,family-chk = "zynquplus";
xlnx,fast-sim-mode = <0x0>;
xlnx,gt-diffctrl-width = <0x4>;
xlnx,gt-drp-clk = "100.00";
xlnx,gt-group-select = "Quad X0Y0";
xlnx,gt-location = <0x1>;
xlnx,gt-ref-clk-freq = "156.25";
xlnx,gt-type = "GTH";
xlnx,gtm-group-select = "NA";
xlnx,include-auto-neg-lt-logic = "None";
xlnx,include-axi4-interface = <0x1>;
xlnx,include-dre ;
xlnx,include-fec-logic = <0x0>;
xlnx,include-hybrid-cmac-rsfec-logic = <0x0>;
xlnx,include-rsfec-logic = <0x0>;
xlnx,include-shared-logic = <0x1>;
xlnx,include-statistics-counters = <0x1>;
xlnx,include-user-fifo = <0x1>;
xlnx,ins-loss-nyq = <0x1e>;
xlnx,lane1-gt-loc = "X1Y14";
xlnx,lane2-gt-loc = "NA";
xlnx,lane3-gt-loc = "NA";
xlnx,lane4-gt-loc = "NA";
xlnx,line-rate = <0xa>;
xlnx,mii-ctrl-width = <0x4>;
xlnx,mii-data-width = <0x20>;
xlnx,num-of-cores = <0x1>;
xlnx,ptp-clocking-mode = <0x0>;
xlnx,ptp-operation-mode = <0x2>;
xlnx,runtime-switch = <0x0>;
xlnx,rx-eq-mode = "AUTO";
xlnx,rxmem = <0x40000>;
xlnx,statistics-regs-type = <0x0>;
xlnx,switch-1-10-25g = <0x0>;
xlnx,tx-latency-adjust = <0x0>;
xlnx,tx-total-bytes-width = <0x4>;
xlnx,xgmii-interface = <0x1>;
xxv_ethernet_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};

 

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