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Registered: ‎08-21-2018

10G Mac Timing failing

Hi all,

I am working with following IPs in my design

  • 10G Ethernet MAC (15.1)
    • 64bits
    • WAN Disabled
    • Priority Flow Control Disabled
  • 10 Ethernet PCS/PMA (6.0)   
    • GTH mode
    • Base R mode
    • RX Elastics Buffer Enabled
    • 64 bits
    • MDIO interface Disabled
    • Refclk & Location are shown with the following diagram.

I am getting a timing failure Slack (Hold) - -0.445ns

 from  mac_2_3/gen_lane[1].i_10G_mac/inst/ten_gig_eth_mac_0_core/tx/tx_sm/tx_fifo_reg_0_3_12_17/RAMA/CLK to mac_2_3/gen_lane[1].i_10G_mac/inst/ten_gig_eth_mac

And My design diagram as follows.

PhyMac Design.png

 

 

Mac 0_1 contains single 10G line and Mac 2_3 contains two 10G lines.

I am getting following timing Error . I have attached the Error Details bellow (Capture.png).

 

My Constrains related to MAC as follows,

 

create_clock -period 10.000 [get_ports clk_in_p]
#set_property IOSTANDARD LVCMOS18 [get_ports clk_in_p]
create_clock -period 6.400 [get_ports gt_refclk_p]

set_max_delay  -datapath_only -from [get_clocks clk_in_p1]       -to [get_clocks gt_refclk_p[0]] $FASTEST_CLK_PERIOD;
set_false_path -hold          -from [get_clocks clk_in_p1]       -to [get_clocks gt_refclk_p[0]];
set_max_delay  -datapath_only -from [get_clocks gt_refclk_p[0]] -to [get_clocks clk_in_p1]       $FASTEST_CLK_PERIOD;
set_false_path -hold          -from [get_clocks gt_refclk_p[0]] -to [get_clocks clk_in_p1];

set_max_delay  -datapath_only -from [get_clocks clk_in_p1]       -to [get_clocks gt_refclk_p[1]] $FASTEST_CLK_PERIOD;
set_false_path -hold          -from [get_clocks clk_in_p1]       -to [get_clocks gt_refclk_p[1]];
set_max_delay  -datapath_only -from [get_clocks gt_refclk_p[1]] -to [get_clocks clk_in_p1]       $FASTEST_CLK_PERIOD;
set_false_path -hold          -from [get_clocks gt_refclk_p[1]] -to [get_clocks clk_in_p1];





set_property LOC GTHE3_COMMON_X0Y2   [get_cells -hierarchical -filter {PRIMITIVE_TYPE==ADVANCED.GT.IBUFDS_GTE3 && NAME =~*mac_0_1[0]*}]
set_property LOC GTHE3_COMMON_X0Y2   [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_COMMON && NAME=~*mac_0_1[0]*}];
set_property LOC GTHE3_CHANNEL_X0Y8  [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_CHANNEL && NAME=~*mac_0_1[0].gen_lane[0]*}];

set_property LOC GTHE3_COMMON_X0Y3   [get_cells -hierarchical -filter {PRIMITIVE_TYPE==ADVANCED.GT.IBUFDS_GTE3 && NAME =~*mac_2_3[0]*}]
set_property LOC GTHE3_COMMON_X0Y3   [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_COMMON && NAME=~*mac_2_3[10]*}];
set_property LOC GTHE3_CHANNEL_X0Y12 [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_CHANNEL && NAME=~*mac_2_3[0].gen_lane[0]*}];
set_property LOC GTHE3_CHANNEL_X0Y13 [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_CHANNEL && NAME=~*mac_2_3[0].gen_lane[1]*}];


set_property LOC GTHE3_COMMON_X1Y2   [get_cells -hierarchical -filter {PRIMITIVE_TYPE==ADVANCED.GT.IBUFDS_GTE3 && NAME =~*mac_0_1[0]*}]  #gen_qsfp
set_property LOC GTHE3_COMMON_X1Y2   [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_COMMON && NAME=~*mac_0_1[0]*}];
set_property LOC GTHE3_CHANNEL_X1Y8  [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_CHANNEL && NAME=~*mac_0_1[0].gen_lane[0]*}];


set_property LOC GTHE3_COMMON_X1Y3   [get_cells -hierarchical -filter {PRIMITIVE_TYPE==ADVANCED.GT.IBUFDS_GTE3 && NAME =~*mac_2_3[0]*}]
set_property LOC GTHE3_COMMON_X1Y3   [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_COMMON && NAME=~*mac_2_3[0]*}];
set_property LOC GTHE3_CHANNEL_X1Y12 [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_CHANNEL && NAME=~*mac_2_3[0].gen_lane[0]*}];
set_property LOC GTHE3_CHANNEL_X1Y13 [get_cells -hier -filter {PRIMITIVE_TYPE=~ADVANCED.GT.GTHE3_CHANNEL && NAME=~*mac_2_3[0].gen_lane[1]*}];


create_pblock -quiet AG_qsfp0_phy0;
add_cells_to_pblock AG_qsfp0_phy0 [get_cells -hier -filter {NAME=~*mac_0_1[0].gen_lane[0]*}];
resize_pblock AG_qsfp0_phy0 -add SLICE_X101Y105:SLICE_X142Y119;
resize_pblock AG_qsfp0_phy0 -add RAMB36_X13Y21:RAMB36_X17Y23;
resize_pblock AG_qsfp0_phy0 -add RAMB18_X13Y42:RAMB18_X17Y47;
set_property exclude_placement 1 [get_pblock AG_qsfp0_phy0];

create_pblock -quiet AG_qsfp1_phy0;
add_cells_to_pblock AG_qsfp1_phy0 [get_cells -hier -filter {NAME=~*mac_2_3[0].gen_lane[0]*}];
resize_pblock AG_qsfp1_phy0 -add SLICE_X101Y165:SLICE_X142Y179;
resize_pblock AG_qsfp1_phy0 -add RAMB36_X13Y33:RAMB36_X17Y35;
resize_pblock AG_qsfp1_phy0 -add RAMB18_X13Y66:RAMB18_X17Y71;
set_property exclude_placement 1 [get_pblock AG_qsfp1_phy0];

create_pblock -quiet AG_qsfp1_phy1;
add_cells_to_pblock AG_qsfp1_phy1 [get_cells -hier -filter {NAME=~*mac_2_3[0].gen_lane[1]*}];
resize_pblock AG_qsfp1_phy1 -add SLICE_X101Y180:SLICE_X142Y194;
resize_pblock AG_qsfp1_phy1 -add RAMB36_X13Y36:RAMB36_X17Y38;
resize_pblock AG_qsfp1_phy1 -add RAMB18_X13Y72:RAMB18_X17Y77;
set_property exclude_placement 1 [get_pblock AG_qsfp1_phy1];


######################################################################
# QSFP 0
######################################################################

set_property PACKAGE_PIN V5 [get_ports {gt_refclk_n[0]}]
set_property PACKAGE_PIN V6 [get_ports {gt_refclk_p[0]}]
#set_property PACKAGE_PIN V5 [get_ports CLK_QSFP0_OSC_OUTN]
#set_property PACKAGE_PIN V6 [get_ports CLK_QSFP0_OSC_OUTP]
set_property PACKAGE_PIN AE21 [get_ports QSFP0_INTN]
set_property PACKAGE_PIN AF12 [get_ports QSFP0_LPMODE]
set_property PACKAGE_PIN AE26 [get_ports QSFP0_MODPRSN]
set_property PACKAGE_PIN AJ13 [get_ports QSFP0_MODSELN]
set_property PACKAGE_PIN AJ11 [get_ports {QSFP0_OSC_FS[0]}]
set_property PACKAGE_PIN AF10 [get_ports {QSFP0_OSC_FS[1]}]
set_property PACKAGE_PIN AE12 [get_ports QSFP0_RESETN]
set_property PACKAGE_PIN AD11 [get_ports QSFP0_SCL]
set_property PACKAGE_PIN AE11 [get_ports QSFP0_SDA]

set_property PACKAGE_PIN Y2 [get_ports {QSFP0_RXP[0]}]
set_property PACKAGE_PIN Y1 [get_ports {QSFP0_RXN[0]}]
set_property PACKAGE_PIN AA4 [get_ports {QSFP0_TXP[0]}]
set_property PACKAGE_PIN AA3 [get_ports {QSFP0_TXN[0]}]

#set_property PACKAGE_PIN V2             [get_ports {QSFP0_RXP[1]}]
#set_property PACKAGE_PIN V1             [get_ports {QSFP0_RXN[1]}]
#set_property PACKAGE_PIN W4             [get_ports {QSFP0_TXP[1]}]
#set_property PACKAGE_PIN W3             [get_ports {QSFP0_TXN[1]}]

#set_property IOSTANDARD LVDS            [get_ports {CLK_QSFP0_OSC_OUT*}];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_INTN]
set_property DRIVE 8 [get_ports QSFP0_INTN]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP0_LPMODE]
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_MODPRSN]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP0_MODSELN]
set_property IOSTANDARD LVCMOS25 [get_ports {QSFP0_OSC_FS[*]}]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP0_RESETN]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP0_SCL]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP0_SDA]



######################################################################
# QSFP 1
######################################################################


set_property PACKAGE_PIN P5 [get_ports {gt_refclk_n[1]}]
set_property PACKAGE_PIN P6 [get_ports {gt_refclk_p[1]}]

set_property PACKAGE_PIN AH13 [get_ports QSFP1_INTN]
set_property PACKAGE_PIN AK11 [get_ports QSFP1_LPMODE]
set_property PACKAGE_PIN AM9 [get_ports QSFP1_MODPRSN]
set_property PACKAGE_PIN AK13 [get_ports QSFP1_MODSELN]
set_property PACKAGE_PIN AG11 [get_ports {QSFP1_OSC_FS[0]}]
set_property PACKAGE_PIN AH11 [get_ports {QSFP1_OSC_FS[1]}]
set_property PACKAGE_PIN AL13 [get_ports QSFP1_RESETN]
set_property PACKAGE_PIN AE13 [get_ports QSFP1_SCL]
set_property PACKAGE_PIN AF13 [get_ports QSFP1_SDA]

set_property PACKAGE_PIN M2 [get_ports {QSFP1_RXP[0]}]
set_property PACKAGE_PIN M1 [get_ports {QSFP1_RXN[0]}]
set_property PACKAGE_PIN N4 [get_ports {QSFP1_TXP[0]}]
set_property PACKAGE_PIN N3 [get_ports {QSFP1_TXN[0]}]

set_property PACKAGE_PIN L3 [get_ports {QSFP1_TXN[1]}]
set_property PACKAGE_PIN K2 [get_ports {QSFP1_RXP[1]}]
set_property PACKAGE_PIN K1 [get_ports {QSFP1_RXN[1]}]
set_property PACKAGE_PIN L4 [get_ports {QSFP1_TXP[1]}]

#set_property IOSTANDARD LVDS            [get_ports {CLK_QSFP0_OSC_OUT*}];
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_INTN]
set_property DRIVE 8 [get_ports QSFP1_INTN]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_LPMODE]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_MODPRSN]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_MODSELN]
set_property IOSTANDARD LVCMOS25 [get_ports {QSFP1_OSC_FS[*]}]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_RESETN]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_SCL]
set_property IOSTANDARD LVCMOS25 [get_ports QSFP1_SDA]


 

Could you please help me to fix the timing issues?

 

PS : I could successfully passed the timing while using single MAC2 & PCS/PMA in X0Y13.

Vivado version 2017.2

 

Thanks in Advance

/Vishwa

Capture.PNG
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