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Adventurer
Adventurer
670 Views
Registered: ‎11-26-2018

10G ethernet subsystem on zcu106

I've some problems with petalinux boot, I get some warnings and errors:

xilinx_axienet a0041000.ethernet: missing/invalid xlnx,addrwidth property, using default
xilinx_axienet a0041000.ethernet: couldn't find phy i/f

and when the eth0 goes up I get these errors:

xilinx_axienet a0041000.ethernet eth0: __axienet_device_reset: DMA reset timeout!
xilinx_axienet a0041000.ethernet eth0: __axienet_device_reset: DMA reset timeout!
xilinx_axienet a0041000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration

The gt ref clock is 156.25MHz and in the system-user I set the mac address for the eth:

&xxv_ethernet_0 {
	local-mac-address = [00 0a 35 00 00 00];
};

I don't know if it's a petalinux configuration problem or a design error.

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17 Replies
Xilinx Employee
Xilinx Employee
591 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hello andrea@ross 

 

Why don't you try using the ZCU106 boot image below?

Zynq Release

 

Thank you

Yoichi

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Adventurer
Adventurer
531 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

Hi, @katsuki 

I fixed the error (it was a design mistake)

XXV MAC block lock not complete! Cross-check the MAC ref clock configuration 

 but now at boot I get a kernel panic:

Configuring network interfaces... [    8.217270] Internal error: synchronous external abort: 96000010 [#1] SMP
[    8.224044] Modules linked in: al5d(O) al5e(O) allegro(O) xlnx_vcu_clk xlnx_vcu xilinx_hdmi_rx(O) xlnx_vcu_core xilinx_vphy(O) video(O) mali(O) uio_pdrv_genirq
[    8.238310] CPU: 0 PID: 2548 Comm: ip Tainted: G           O      4.19.0-xilinx-v2019.1 #1
[    8.246562] Hardware name: ZynqMP ZCU106 RevA (DT)
[    8.251338] pstate: 60000005 (nZCv daif -PAN -UAO)
[    8.256118] pc : axienet_device_reset+0x258/0x2e0
[    8.260809] lr : axienet_open+0x2ec/0x598
[    8.264800] sp : ffffff8010cbb210
[    8.268099] x29: ffffff8010cbb210 x28: ffffffc879d07d00
[    8.273403] x27: ffffff8010cbb830 x26: ffffff8010cbbaf0
[    8.278707] x25: ffffff8008be0858 x24: 0000000000000000
[    8.284002] x23: 0000000000000002 x22: ffffffc87a4e6048
[    8.289298] x21: ffffff8008be0858 x20: ffffffc87a4e6000
[    8.294593] x19: ffffffc87a4e67c0 x18: 0000000000000000
[    8.299888] x17: 0000000000000003 x16: 0000000000000000
[    8.305183] x15: 0000000000000000 x14: 0000000000000000
[    8.310479] x13: 0000000000000000 x12: 0000000000000000
[    8.315774] x11: 0000000000000000 x10: 0000000000000000
[    8.321069] x9 : 0000000000000000 x8 : ffffff8010cbb9d0
[    8.326365] x7 : 0000000000000000 x6 : 0000000000000000
[    8.331660] x5 : ffffff8010cbb9d0 x4 : 0000000000000000
[    8.336955] x3 : ffffff800898ab18 x2 : 0000000000000000
[    8.342251] x1 : ffffff8008035000 x0 : 0000000000000003
[    8.347548] Process ip (pid: 2548, stack limit = 0x(____ptrval____))
[    8.353883] Call trace:
[    8.356316]  axienet_device_reset+0x258/0x2e0
[    8.360656]  axienet_open+0x2ec/0x598
[    8.364303]  __dev_open+0xd4/0x150
[    8.367697]  __dev_change_flags+0x154/0x1b8
[    8.371863]  dev_change_flags+0x20/0x60
[    8.375684]  do_setlink+0x288/0xb90
[    8.379164]  rtnl_newlink+0x3d8/0x6b0
[    8.382810]  rtnetlink_rcv_msg+0x218/0x300
[    8.386891]  netlink_rcv_skb+0x58/0x118
[    8.390709]  rtnetlink_rcv+0x14/0x20
[    8.394269]  netlink_unicast+0x1c4/0x258
[    8.398175]  netlink_sendmsg+0x164/0x338
[    8.402081]  sock_sendmsg+0x18/0x30
[    8.405553]  ___sys_sendmsg+0x268/0x2a0
[    8.409373]  __sys_sendmsg+0x68/0xb8
[    8.412932]  __arm64_sys_sendmsg+0x20/0x28
[    8.417014]  el0_svc_common+0x84/0xd8
[    8.420667]  el0_svc_handler+0x68/0x80
[    8.424400]  el0_svc+0x8/0xc
[    8.427266] Code: d2800060 9411a785 17fffff5 f9401261 (b9400020)
[    8.433350] ---[ end trace ba28dd59009edade ]---

 

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Xilinx Employee
Xilinx Employee
523 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hi andrea@ross 

 

I'm afraid, I don't know anything about your design.

 

To get to the cause,

1. Make a simple and easy design and make sure it works

2. Check the operation while adding the functions you need to the above design little by little

 

then,  you can narrow down the cause.

 

Thanks

Yoichi

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Adventurer
Adventurer
471 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

I solved the problem rebuilding the petalinux project. The link is up, but when I try to send some packets or to ping the zcu106 from the pc the ping fails, the zcu is not reachable or the ps doesn't receive the packet.sfp.JPG

 

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Xilinx Employee
Xilinx Employee
399 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hello andrea@ross 

 

Are the IP address of the ZCU106 Ethernet and your PC correct? Are they the same subnet mask?

 

Thank you

Yoichi

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Adventurer
Adventurer
359 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

Hi @katsuki ,

yes, the pc and the zcu106 are in the same network and the addresses are correct, but after some tests I get the kernel panic again. I don't know why.

Andrea

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Xilinx Employee
Xilinx Employee
341 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hello andrea@ross 

 

Can you narrow down the cause?

What should you do to narrow down the cause?

 

Thank you

Yoichi

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Adventurer
Adventurer
332 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

Hello, @katsuki 

I can't narrow down the cause, because from the previous version I never change anythings, only some setting of the 10g/25 ip. I tried to use a previus version where there was no kernel panic error, but now also with that version appears the kernel panic.I tried to create a new petalinux project, but it continues to do kernel panic. Now I'm trying to create a new design project.

 

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Adventurer
Adventurer
316 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

From the kernel panic stack it seems that the error occurs when the driver does axienet_device_reset

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Xilinx Employee
Xilinx Employee
302 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hello andrea@ross 

 

Is the previous version of the design a Xilinx example or your own?

Are the Vivado versions the same?

Are the versions of Vivado and Petalinux the same?

 

What is the difference from the previous version?

What did you change in the IP settings?

 

Thank you

Yoichi

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Kindly note - Please mark the Answer as "Accept as solution" if information provided is helpful.
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Adventurer
Adventurer
298 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

The previous version is my design, the vivado version is the same 2019.1 and petalinux 2019.1. From the previus design I chanegd only the axi_lite clk of the ip and the GT lane from X0Y8 to X0Y10 (maybe this is the correct). I attach the design below.

Thank you,

Andrea

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Xilinx Employee
Xilinx Employee
248 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hello andrea@ross 

 

What if you only change the axi_lite_clk for the previous version that is running?

What if you only change the GT lane for the previous version that is running?

 

Thank you

Yoichi

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Kindly note - Please mark the Answer as "Accept as solution" if information provided is helpful.
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Adventurer
Adventurer
210 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

If I change the GT lane, the error persist, in the previous version the axi_lite was connected to the wrong clock and I couldn't read the registers correctly.

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Adventurer
Adventurer
203 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

"good" news, after some rebuild of petalinux I resolved the kernel panic, but now I get the error

Configuring network interfaces... [   10.861519] xilinx_axienet a0042000.ethernet eth0: __axienet_device_reset: DMA reset timeout!
[   10.871488] xilinx_axienet a0042000.ethernet eth0: __axienet_device_reset: DMA reset timeout!
[   10.881755] xilinx_axienet a0042000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration

with the scui I checked the si570 user clock and is configured correctly (156.25MHz).eth.JPG

Thank you,
Andrea

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Adventurer
Adventurer
176 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

I managed to make it work, the only thing I can't make work correctly is the si570 clock. During the boot I find this:

[    5.388165] i2c i2c-1: Added multiplexed i2c bus 7
[    5.393146] i2c i2c-1: Added multiplexed i2c bus 8
[    5.411999] si570 9-005d: registered, current frequency 156250000 Hz
[    5.418375] i2c i2c-1: Added multiplexed i2c bus 9
[    5.425154] si570 10-005d: registered, current frequency 156250000 Hz
[    5.431620] i2c i2c-1: Added multiplexed i2c bus 10
[    5.436685] si5324 11-0069: si5328 probed
[    5.501122] si5324 11-0069: si5328 probe successful

Seems the chip is configured correctly, but at the end of the boot I get this error:

xilinx_axienet a0042000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration

if I use the zcu106 scui I read the correct clocks 

scu.JPG

but only after I set (from the scui) the user clock to 156.25MHz the system start working. 

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Xilinx Employee
Xilinx Employee
158 Views
Registered: ‎11-05-2019

Re: 10G ethernet subsystem on zcu106

 

Hello andrea@ross 

 

If the output clock frequency of si570 is different from the expected value, it may be better to check the device tree.

 

Thank you

Yoichi

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Adventurer
Adventurer
137 Views
Registered: ‎11-26-2018

Re: 10G ethernet subsystem on zcu106

Hello @katsuki 

From the petalinux boot seems that the os change the frequency, inside system-user.dts I put this lines:

&i2c1{
	status = "okay";
	i2c-mux@74 {
		i2c@2 {
			si570_1: clock-generator@5d { /* USER SI570 - u42 */
				factory-fout = <300000000>;
				clock-frequency = <156250000>;
				clock-output-names = "si570_user";
			};
		};
		i2c@3 {
			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
				factory-fout = <156250000>;
				clock-frequency = <156250000>;
				clock-output-names = "si570_mgt";
			};
		};
		i2c@4 {
			si5328: clock-generator@69 {
				compatible = "silabs,si5328";
				clock-frequency = <156250000>;
			};
		};
	};
};

It seems working, because I see from the boot that the frequencies are correct, but it seems that they are not applied.

Andrea