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Adventurer
Adventurer
474 Views
Registered: ‎10-17-2018

10G ethernet subsystem reset pins are confuse

Hi, I'm trying to use the 10G ethernet subsystem on my VC707 board but I don't know how to properly connect the following pins : 

2019-03-11-143758_385x564_scrot.png

  1. tx_axis_aresetn : I've connected to mm2s_prmy_reset_out of AXI2S FIFO(I think it's right)
  2. rx_axis_arestn: I've connected to s2mms_prmy_reset_out of AXI2S FIFO(I also think it's right)
  3. s_axi_aresetn: I've connected to peripheral_aresetn of my design(as I did for the others IPs, so I think it's right)
  4. reset: I've no idea about where connect it

Reading the datasheet of the IP, I found :

The reset input provides an active-High global asynchronous reset input that resets
everything in the design, including the transceiver and associated PLLs.
Each of the interface resets (s_axi_aresetn, tx_axis_aresetn, and
rx_axis_aresetn), apply local resets to sub-blocks of the overall design. These resets
should not be required in normal operation or implementation.

But I still don't know how to use that port(reset)

 

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2 Replies
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Moderator
Moderator
419 Views
Registered: ‎11-09-2017

Hi @jamellyf 

Reset is active high global asynchronous reset, this port can be connected to system reset, for example you can conncet to push bottom.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

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Adventurer
Adventurer
408 Views
Registered: ‎10-17-2018

Hey, @rpr can I connect it to the peripheral_reset[0:0] port of the Processor System Reset IP?

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