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Observer
Observer
118 Views
Registered: ‎11-24-2020

10GE Example Design - XDC

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Hi,

In the 10G Ethernet example design for the Xilinx core generator IP, are the timing and pin constraints already included. I am running Vivado in GUI mode and I cannot see any constants when running the constraints wizard and non of the .xdc files are automatically added to the project.  However, the IP generated files in the project folder contains several .xdc files with constraints. 

The design was successful in a basic simulation. Will the design run just this way on the board, the bit file generation was successful. I don't have the exact board I have used to try this, thus asking.

Thanks in Advance

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Moderator
Moderator
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Registered: ‎08-21-2007

Are you using the 10G Ethnet Subsystem ? I find there's xdc file generated in the IP example design project.

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Moderator
Moderator
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Registered: ‎07-31-2012

@dharpeer ,

The 10G example design will run on most of the board part but again you need to check the IO pin constraints if it is applicable on the selected device.

 

Regards

Praveen


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Observer
Observer
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Registered: ‎11-24-2020

Hi Praveen,

So I guess the timing constraints are already contained?

 

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Moderator
Moderator
77 Views
Registered: ‎08-21-2007

Are you using the 10G Ethnet Subsystem ? I find there's xdc file generated in the IP example design project.

-----------------------------------------------------Please don't forget to give kudos or accept as solution if information provided is helpful.---------------------------------------------------------------------

View solution in original post

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