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user-1042
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Registered: ‎02-18-2021

10g Example in ZCU102

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I have two ZCU-102 boards loaded with prebuilt images from:

https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet/tree/main/2019.2/pl_eth_10g

The two boards are connected using the top right of the 2x2 SFP cage with a direct attach copper cable.

I think the boards boot up just fine and I can get in via serial port to both boards just fine. However, they can't ping to each other. My workflow is the following...

Connect serially to both boards (turned off)

Turn on both of the boards. Boot up starts (not sure if weird but I get this strange line: ethernet@ffe0000 Waiting for PHY auto negotiation to complete ............ TIMEOUT !)

Log onto root on both boards.

>> ifconfig eth1 192.168.0.1 # on board 1

>> ifconfig eth1 192.168.0.2 # on board 2

>> ping 192.168.0.2 # on board 1

But the ping hangs. Help!

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user-1042
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Registered: ‎02-18-2021

In case other people run into this issue,

XXV MAC block lock not complete! Cross-check the MAC ref clock configuration

meant for me was that the gt_ref_clk wasn't syncing. I used the SCUI tool to set si470 to 156.25MHz, then it worked.

View solution in original post

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hpbhat
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Registered: ‎02-08-2021

Hi,

https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet/tree/main/2019.2/pl_eth_10g

In the above link, the ethernet is tested using DHCP. But, I understand that you are connecting board to board [Static IP]. During auto-negotiation, the board is not able to connect to DHCP, time out is happening.

Since, auto negotiation is failed, there is no point in testing ping as auto negotiation fail means the ethernet link is not established. That's the reason why ping hangs.

This is the one reference on similar problem discussion. https://unix.stackexchange.com/questions/122921/gem-e000b000-waiting-for-phy-auto-negotiation-to-complete-timeout

With Regards,

HPB

user-1042
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Registered: ‎02-18-2021

Are you sure it's not supposed to work board to board? I saw a forum post that someone was able to do so:

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/XAPP1305-PL-10G-SFP-ready-to-test-files-failing-with-quot-couldn/td-p/767137

To add error messages to debug help debug I get this error when bringing up eth1:

xilinx_axienet a0041000.ethernet eth0: __axienet_device_reset: DMA reset timeout!
xilinx_axienet a0041000.ethernet eth0: __axienet_device_reset: DMA reset timeout!
xilinx_axienet a0041000.ethernet eth0: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration
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user-1042
Visitor
Visitor
328 Views
Registered: ‎02-18-2021

In case other people run into this issue,

XXV MAC block lock not complete! Cross-check the MAC ref clock configuration

meant for me was that the gt_ref_clk wasn't syncing. I used the SCUI tool to set si470 to 156.25MHz, then it worked.

View solution in original post

nanz
Moderator
Moderator
257 Views
Registered: ‎08-25-2009

Hi @user-1042 ,

Good to hear the issue is resolved. Could you please mark the above thread as accepted solution so it will benefit other forum users. Thank you!


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