05-01-2017 04:00 PM
Just a small issue,
I am trying to get the gtrefclk_out_bufg running on ZC706 hardware.
I suppose jit_att_mgt_clk and sysdiff_clk are generated from the board.
All I need to do is give proper reset, configuration vectors.
1. signal_detect is set to 1.
2. reset is tied to SW7 that provides about 1ms of reset.
For now I just wish to run the design on hardware and monitor just the gtrefclk_out_bufg signal.
Can anyone tell me why am I not able to see any output clock on Saleae logic analyzer.
Any help is highly appreciated.
05-01-2017 06:36 PM
I also have another doubt.
Is the mgt_clk/jit_att_mgt_clk dependent on the presence of GTX transceiver active connection?
Because, I haven't connected the above design to a target PCS/PHY. No link is present. It's just the clock I need to monitor.
05-01-2017 09:31 PM - edited 05-01-2017 09:32 PM
You need to use the sysnthesizer mode to program the output clock from the jitter attenuator or drive recovered or reference clock input and use the jitter attenuator in by pass mode and it will not generated any clock output by default.
Check below threads on clock generation
05-03-2017 09:33 AM
Thank you for your response.
I tried to check out the links that you provided.
The link says:
You will need to connect the RECCLK from GT to which the design is targeted to the REC_CLOCK_P and REC_CLOCK_N pins. The synthesizer is set for pass through mode so the output clock is same as the RECCLK output from GT.
To get RECCLK out from FPGA, you need to use ODDR block.
You mentioned about a drive recovered/ref clock input and use the jitter attenuator in a bypass mode. Could you please tell me how this relates to what the link states?
Also I suppose, gtrefclk_in for 1G/2.5G PCS requires 125MHz of clock. With the above settings, is it possible to provide such a clock or I have to program the si5324 registers to generate 125MHz of clock that connects to gtrefclk_in(AC8) via si5324_out_p/n?
05-04-2017 05:21 AM
Si5324 can be used either a clock generator or jitter attenuator.
You need to decide on which mode you want to use and configure it accordingly.
In jitter attenuator mode the input clock should be 125Mhz and for clock generator you need to program the registers to get this frequency.
Refer below doc
You can find reference Si5324 reference design from below link
05-08-2017 10:51 AM
05-08-2017 03:42 PM
I was able to configure the Si5324 chip with 125MHz parameters.
After I write to the chip, I read back the values and they match with 125MHz configuration.
Since there is no way I could monitor the jit_att_mgt_clk (output from Si5324 chip directly), I measured the output at gtrefclk_bufg_out and userclk_out. Both their outputs display 62.5MHz. Whereas the output of gtrefclk_bufg_out, should be 125MHz instead of 62.5MHz of clock.
Your help is highly appreciated.
05-12-2017 03:13 PM