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thaus_015
Explorer
Explorer
631 Views
Registered: ‎03-29-2017

25G Ethernet on Zynq UltraScale+ FPGA (GTY transceiver is not working)

I am using XCZU19EGFFVD1760 FPGA board, and I am checking the 25G Ethernet Speed on Zynq UltraScale+ board with QSFP but GTY transceiver is not working. 

In  10G/25G Ethernet Subsytem IP, I have set the GT selection and configuration according to the documents. 

What could be the problem ? Anyone can suggest please 

Speed : 25G
Enabled : 4 Cores
GT Selection and Configuration : GTY , Clock : 322.265 MHZ. 

Eth25_1.pngGT ConfigGT ConfigRX Window is inactiveRX Window is inactive

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6 Replies
guozhenp
Xilinx Employee
Xilinx Employee
559 Views
Registered: ‎05-01-2013

Is this for simulation?

Please try IP core example design first.

And add "-d SIM_SPEED_UP" to speed up the simulation

Can you see data in simulation?

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thaus_015
Explorer
Explorer
549 Views
Registered: ‎03-29-2017

>>>>Is this for simulation?           NO

After generating bitstream and dupping the .bit file into hardware. Then checking the output in ILA.

 

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guozhenp
Xilinx Employee
Xilinx Employee
538 Views
Registered: ‎05-01-2013

Still you can try IP core example design with near end loopback mode first.

You can also run IBERT first to confirm that GTY HW environment is good.

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thaus_015
Explorer
Explorer
521 Views
Registered: ‎03-29-2017

>>Still you can try IP core example design with near end loopback mode first.

 

Any link please :(

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guozhenp
Xilinx Employee
Xilinx Employee
499 Views
Registered: ‎05-01-2013

Right click on the IP core .xci file in Vivado project and select "generate IP core example design"

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pvenugo
Moderator
Moderator
474 Views
Registered: ‎07-31-2012

Hi @thaus_015 ,

Also, please refer to page 20 for further detail of IBERT example design in  https://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/v1_3/pg196-ibert-ultrascale-gty.pdf.

Regards

Praveen


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