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454 Views
Registered: ‎03-01-2019

40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

Hi,

The user guide https://www.xilinx.com/support/documentation/ip_documentation/l_ethernet/v2_5/pg211-50g-ethernet.pdf

states that for a 256bit wide interface the clock must be 312.5mhz for 40g speed.

If this is true then the actual throughput will be 80g (256x312.5) if the axi4 valid is continuously high.

I would like to know if there is a gap after every valid so that the core gives data at 40g. 

or

Will I get 256bit axi4 interface at 156.25mhz ? If so is there any mention of this anywhere ?

Regards,

Giri

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6 Replies
Xilinx Employee
Xilinx Employee
424 Views
Registered: ‎05-01-2013

回复: 40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

I checked PG211. Both 128bit and 256bit interfaces have the 312.5MHz core clock.

So tx_axis_tready isn't always high. Sometimes it's deasserted to meet the 40G bandwidth.

I suggest you follow the PG to use the 312.5Mhz clock.

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419 Views
Registered: ‎03-01-2019

回复: 40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

Thank you for the response. 

Regarding the dessertion. I understand the packets come into this at 40G rate, but this theoretically means it will deassert every alternate cycle. 

I am building an axi4 simulatior for 256bit 312.5mhz interface for 40g constant bandwidth. So I need to know how often I should deassert the valid. Presently I can even assert it for 100 cycles and deassert it for another 100 cycles. Effectively making it 40g, but during the first 100 cycles it comes in at 80g. 

Can I know what is the maximum cycles it will stay asserted so that my simulator can better test the ip's? If I know this then I can ensure the assertion does not exceed this and over all I can make sure bandwidth does not exceed 40g. 

Thanks a lot.  

 

 

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Xilinx Employee
Xilinx Employee
414 Views
Registered: ‎05-01-2013

回复: 40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

If you mean to TX side, I'm afraid you can't deassert tvalid until the whole packet is completed.

PG211 has the following description.

• An implicit underrun in which a frame transfer is aborted by deasserting tx_axis_tvalid without asserting tx_axis_tlast.

When a packet data transaction has begun in the TX direction, it must continue until completion or there can be a buffer underflow as indicated by the signal tx_unfout. This must not be allowed to occur; data must be written on the TX AXI4-Stream without interruption. Ethernet packets must be present on the line from start to end with no gaps or idles. If tx_unfout is ever asserted, debugging must stop until the condition which caused the underflow has been addressed.

 

Only when tready is deasserted by IP core, you can deassert tvalid.

402 Views
Registered: ‎03-01-2019

回复: 40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

Thank you very much. This is useful. But I was reffering to the RX side.

I wanted to know what is the maximum cycles rx valid will stay continuously asserted ? Based on this I can build the axi4 simulator. 

Is it possible that it can stay asserted for an entire packet. But over all have 40G bandwidth due to larger inter packet gaps ?

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Xilinx Employee
Xilinx Employee
378 Views
Registered: ‎05-01-2013

回复: 40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

Sorry, I'm afraid we don't kown the RX behavior.

IP has its internal buffer.

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337 Views
Registered: ‎03-01-2019

回复: 40G/50G ETHERNET SUBSYSTEM 256BIT INTERFACE CLOCK SPEED

Ok. Thanks. 

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