07-12-2019 01:13 AM
I am just making simulation with 40G Ethernet Subsytem IP Core. I red the datasheet, it is written that low latency mode is available. Then I saw below section. And It is written that 153ns latency occurs in this clocking mode.
Then I opened the Open IP Example Design and tracked the clock signals. I made some changes with clocks but in simulation, again there is 304ns between tx_axis_tvalid and rx_axis_tvalid. How can I reduce latency from 304ns to 153ns.
07-24-2019 01:12 PM