07-11-2019 09:10 AM
When using the 1G/2.5G PCS/PMA IP, and the IP is setup with a physical interface of "LVDS-Serial", there is specific reference to the 625Mhz LVDS reference clock. This LVDS clock is output from the TP Phy device (DP83867) into an LVDS pair on the FPGA
I now want to route a GEMAC out of an MPSoC-PS using a GTR channel, but when I set this up in the PS GUI, there is no reference as to how the 625Mhz LVDS clock from the TI chip is to be fed into the MPSoC. Is this 625Mhz reference clock redundant when using a dedicated gigabit XCVR in the MPSoC (or any Xilinx chip), and if so how do I disable it in the Ti device?
07-22-2019 03:46 AM
PCS/PMA can be implemented either through LVDS IO or GT transceivers.
625MHz only available only through SGMII over LVDS.
However you are for GT you wont find 625MHz.
07-26-2019 12:44 AM
The SGMII specification (I'm reading version 1.7, from 2001) says the clocks (there are two: one Tx, one Rx, each co-directional with its respective data) are optional on the receiver, and almost every SGMII receiver that I've seen works without them. That apparently is also the case with the GTR that you want to use.
This is possible because the data signals are encoded in such a way that CDR is possible from them without needing the clock.
The specification still says the transmit clock is mandatory, which is why your PHY supplies it, even though it will typically not be connected on most boards that uses that PHY.
I haven't looked at the PS GTR, but I would guess that the Xilinx designers did not bother to include the mandatory Tx clock output, on the basis that it would require two pins (expensive!) and no board designer would actually use it.