I am trying to use two AXI 1G/2.5G Ethernet Subsystems in my block design. I specified locations for the SPF rx, tx and CLK to use mgtp0 and mgtp3.
I keep getting this error in implementation:
[Place 30-640] Place Check : This design requires more GTPE2_COMMON cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.
I am using shared logic in core. How can I resolve this?
This is one of the annoyances with how Vivado deal with IP cores. The problem is that the transceivers use a shared PLL block, and there is only one of those PLLs per group of four transceivers. There are a few possible solutions to this: 1. Generate one IP core instance with all of the channels, or at least one per quad. This may or may not be supported by the wizard. 2. Generate one IP core instance per channel, but set one per quad to place the common components "in the core" and the rest to place the common components "in the example design". Then make the necessary connections between the cores (usually a handful of PLL clock and reset connections). 3. Generate the GT instances using the gtwizard as a single core, separately from the higher-level logic (MAC, PCS/PMA, etc.). Let the gtwizard handle all of the transceiver connections, then connect the user logic side of the transceivers to the Ethernet core instances.