06-29-2019 06:23 PM - edited 06-29-2019 06:31 PM
I am trying to transmit packets via 1GE/SFP on the ZCU102. I am not sure if I need the "processor features/mode" available in the AXI 1G Ethernet Subsystem. At this moment, I have the IP core configured for 1000BASE-X with "processor features" disabled, but I am not 100% sure whether I need the features available in processor mode or not.
I have data framed in ethernet packets (MAC source/dest, ethernet type, etc...) being fed to the core's TX interface (s_axis_tx), and I have an external SFP->fiber loopback. Finally, I am feeding the receive signals (m_axis_rx) to an ILA just to observe the received data. I have not successfully received any data.
So, I am trying to understand the different modes of this core. I have read through the documentation for the subsystem, its sub-IPs, and XAPP1082 and XAPP1305, but I cannot seem to get this working.
In what cases would I need "processor mode" and in what cases can I get away without using it?
As a bonus: any advice for using this core in "non-processor mode" 1000BASE-X?
As a double bonus: which SFP in the ZCU102's cage is SFP0???
I appreciate any and all help!
07-01-2019 02:16 AM
In ILA have you observed TX data? issue is only with RX data?
Ensure that the polarities of the txn/txp and rxn/rxp lines are not reversed.
Internal loopback provided by core you can check with it.
07-22-2019 07:08 AM
I have not observed any data for TX nor for RX. I double checked the polarities of txn/p and rxn/p. I had trouble configuring the core for internal loopback. Assistance with doing that would be appreciated.
I am not using any driver right now. Primarily, I am wondering if I am using the core in the right way (non-processor mode), and if I need to include the linux driver (and therefore the ethernet subsystem in the device tree) when using this in non-processor mode.
07-23-2019 02:28 AM
Do you run the IP core example design?
Have you done the simulation and is able to see the data in simulation?
07-23-2019 08:12 AM
Yes, I ran the IP core example design, but I am trying to figure out whether that design requires/includes drivers in software for controlling the IP core's AXI LITE interface and maybe for initializing an ethernet link.
I have simulated the rest of my design, but not the IP core itself.