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Visitor
Visitor
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Registered: ‎12-16-2019

AXI Ethernet FIFO Full Checksum Offload

Hi, I have a system consisting of AXI Stream FIFO, Microblaze and AXI Ethernet. I have implemented basic protocols like ICMP, UDP and ARP by calculating checksum in Microblaze. I am wondering how can I access "configuration words" to implement "full checksum offload". There is not enough information for this on the Internet or user guides. Could you help me please?

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Moderator
Moderator
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Registered: ‎08-25-2009

Re: AXI Ethernet FIFO Full Checksum Offload

Hi @mertsalar137 ,

Have you refered to PG138 - "Full TCP/UDP Checksum Offload in Hardware"?

Can you please be more specific on what is not clear?

Can yoll

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Visitor
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Registered: ‎12-16-2019

Re: AXI Ethernet FIFO Full Checksum Offload

Yes, I have almost memorized PG138. I have also checked AXI FIFO Stream user guide and TEMAC user guide. However, there is nothing about controlling “configuration words”. I am not at work now but tomorrow I can share my block design, but is is really simple consisting of Microblaze, AXI Streaming FIFO and Axi Ethernet IP. My problem is that I do not know how to access these 6 configuration words (APP0-6) by programming Microblaze.

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Moderator
Moderator
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Registered: ‎08-25-2009

Re: AXI Ethernet FIFO Full Checksum Offload

Hi @mertsalar137 ,

It says in PG138 -

"If the transmit AXI4-Stream control word bits 1:0 are 00 (TX_CSCNTRL is disabled) or if the parameter C_TXCSUM is 0 (the transmit checksum offload function is not included in build), then none of the transmit AXI4-Stream control words are used and no transmit checksum offload takes place. If the parameter C_TXCSUM is 1, transmit partial checksum offload can be controlled on a frame-by-frame basis by setting or clearing the transmit AXI4-Stream control word 1 bits 1:0 to 01 (TX_CSCNTRL). If the parameter C_TXCSUM is 2, the transmit full checksum offload can be controlled on a frame-by-frame basis by setting or clearing the transmit AXI4-Stream control word 1 bits 1:0 to 10 (TX_CSCNTRL)."

 

 

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Visitor
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Registered: ‎12-16-2019

Re: AXI Ethernet FIFO Full Checksum Offload

Yes, it says. Butt does not say how to set TX_CSUM. My problem is that I cannot find any method to set these parameters with Microblaze because they do not have addresses like register space.

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Explorer
Explorer
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Registered: ‎04-07-2014

Re: AXI Ethernet FIFO Full Checksum Offload

Hi,

inside your blockdesign you should use the following commands:

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.1 axi_ethernet_0

set_property -dict [list CONFIG.TXCSUM {Full} CONFIG.RXCSUM {Full}] [get_bd_cells axi_ethernet_0]

TEMAC is part of that ethernet subsystem. The CRC offloading is realized inside the AXI Ethernet Buffer and not inside TEMAC.

In SDK or Vitis setup the Board Support Package:
Use LWIP
Go to LWIP -> temac_adapter_options
There you can setup the CRC offloading.

Hope that helps,

Sebastian

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Visitor
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Registered: ‎12-16-2019

Re: AXI Ethernet FIFO Full Checksum Offload

Thank you very much. I will try it tomorrow. If it works or not, I will tell it in my post and accept the solution.

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Moderator
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Registered: ‎08-25-2009

Re: AXI Ethernet FIFO Full Checksum Offload

Hi @mertsalar137 ,

Here is how to configure the core.

Capture.PNG

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Visitor
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Registered: ‎12-16-2019

Re: AXI Ethernet FIFO Full Checksum Offload

I have already configured the core as full checksum. My problem is that I do not know which interface I should use to configure "configuration words". The first image that I have uploaded is taken from page 105 of PG138 and they are the "configuration words" which I have mentioned. The second image taken from page 112 of PG138 shows TxC interface of AXI Ethernet to configure "configuration words" but this is for DMA, not for FIFO. I am wondering that is there a method to config "configuration words" not through VHDL but Microblaze. I do not want to break the logic of TxC interface between FIFO and Axi Ethernet as shown in third image which is my block design.

Capture.JPG

Capture2.JPG

 

Capture3.JPG

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Explorer
Explorer
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Registered: ‎04-07-2014

Re: AXI Ethernet FIFO Full Checksum Offload

Hi Mertsalar,

I operated ethernet subsystem only with DMA and the light weight IP Stack called "LWIP". When I understand you correctly, you have no external RAM in your design and you try to get an even ligther IP solution running only with microblaze, some FIFO and the ethnet itself.

Unfortunatelly my experience lies with the external RAM and DMA approach.

The source code of the LWIP driver might give you some hint, how to set the configuration registers correctly?

Good luck,

Sebastian

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