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Visitor
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Registered: ‎04-02-2019

AXI Ethernet IP on Zynq Ultrascale+ (GMII)

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Hello,

I want to implement the AXI Ethernet IP Core into my design. The PHY that it has to connect to works via RGMII. However, the reference design I'm using: https://download.enclustra.com/public_files/SoC_Modules/Mercury_XU5/Mercury_XU5_Reference_Design_for_Mercury_PE1_V6.zip

already made a conversion from GMII to RGMII. So the physical pin mapping will be done via GMII where the conversion from GMII to RGMII is done in hardware. I know that I can select the GMII option in the AXI Ethernet IP but then the pins don't match. See picture below. (Left picture is the Ethernet IP, the right one are the external interface pins). Some pins correspond but pins such as gmii_col and gmii_crs don't.

GMII-axi-ethernet.pngGMII-pins.png

Can someone point me in the right direction as to how I should approach this problem? I tried making the connection to RGMII directly but then it conflicts with constraints made in the reference design.

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Registered: ‎11-09-2017

Re: AXI Ethernet IP on Zynq Ultrascale+ (GMII)

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Hi @dnr1406 

col & crs ports enabled for half duplex mode, xilinx TEMAC supports both full and half duplex modes.

AXI ethernet subsystem supports only full duplex.

Regards
Pratap

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Registered: ‎11-09-2017

Re: AXI Ethernet IP on Zynq Ultrascale+ (GMII)

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Hi @dnr1406 

col & crs ports enabled for half duplex mode, xilinx TEMAC supports both full and half duplex modes.

AXI ethernet subsystem supports only full duplex.

Regards
Pratap

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