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achaddha
Observer
Observer
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Registered: ‎05-13-2015

AXI_Ethernet Lite Not Working

Run into the following problem, appreciate any help.

Vivado 19.2, instantiate AXI_Ethernet Lite on a block diagram along with other components (microblaze, mig, frame buffers etc).

Block diagram checks out fine. Synthesis fails with message below (total 5 such messages)

[Synth 8-485] no port 'I' on instance ["/home/achaddha/projects/Airs/nuc/xilinx_ip/frmbuf_mblaze/frmbuf_mblaze.srcs/sources_1/bd/frmbuf_mblaze_1/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":13906]
[Synth 8-485] no port 'I' on instance ["/home/achaddha/projects/Airs/nuc/xilinx_ip/frmbuf_mblaze/frmbuf_mblaze.srcs/sources_1/bd/frmbuf_mblaze_1/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":13906]

Clicking on the message points to this --

-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF

port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);

RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
----

The IBUF component in this Vivado generate file uses i, o not I and O like the other components. I tried changing it but made no difference.

Intention is to use this on the Arty-A7-100 board for testing before building board. Thanks.

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7 Replies
nanz
Moderator
Moderator
643 Views
Registered: ‎08-25-2009

Hi @achaddha ,

It looks like there is a define of "I" port on axi_ethernetlite IP somewhere else but it does not actually match what is available on the IP. Is this the case?

Can you please show a block diagram of your design? I am not sure which block is looking to find this "I" port.

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achaddha
Observer
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Registered: ‎05-13-2015

I think you may be correct. Here is the process I followed --

1. Take lightweight IP design from Arty-7T-35 from here using Vivado_2015.2

https://www.avnet.com/shop/us/products/avnet-engineering-services/aes-a7mb-7a35t-g-3074457345635221621/

This worked fine. Synthesis is OK.

2. Converted the board to Arty-7T-100 (bigger FPGA).

This worked fine. Synthesis is OK.

3. Switched to Vivado_2019.2

This worked fine. Synthesis is OK.

4. Now added two frame read buffers and one write buffer (now it is a new block diagram) which is attached.

This is where I got the error

[Synth 8-485] no port 'i' on instance ["/home/achaddha/projects/Airs/nuc/xilinx_ip/frmbuf_mblaze/frmbuf_mblaze.srcs/sources_1/bd/frmbuf_mblaze_1/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":13907]
[Synth 8-485] no port 'i' on instance ["/home/achaddha/projects/Airs/nuc/xilinx_ip/frmbuf_mblaze/frmbuf_mblaze.srcs/sources_1/bd/frmbuf_mblaze_1/ipshared/cae2/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd":13907]

I suspect the buffers use IOBUF from somewhere else which are different from those used by the Ethernet light IP (Note both are from Xilinx). However, how do I get past this problem?

Attached is the tcl and pdf file.

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nanz
Moderator
Moderator
550 Views
Registered: ‎08-25-2009

Hi @achaddha ,

I have run into the following errors with your tcl file. 

Capture.PNG

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achaddha
Observer
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Registered: ‎05-13-2015

The tcl and pdf files are generated by vivado. Not sure why you are getting the error different from mine. Could you go through the steps I went through and described earlier. It should only take a few minutes. As you said there is a conflict in the two IPs on the diagram.

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nanz
Moderator
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467 Views
Registered: ‎08-25-2009

Hi @achaddha ,

I am not what happened on my local PC but when I switch a PC and re-implement the design, I do not see any synthesis errors.

The following errors are seen just because I do not have the constraints files.

Capture.PNG

 

 

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dgisselq
Scholar
Scholar
445 Views
Registered: ‎05-21-2015

@achaddha ,

Beware when you use the AXI ethernet-lite core that it has some serious AXI bugs within it that Xillinx has not fixed as of Vivado 2020.1.  These problems might cause it to either hang, or if given both read and write addresses--it might cause any writes to the core to be applied to the read address.

You might wish to ask Xilinx to fix these bugs if the core is important to you.  I asked them over a year ago, however, and ... they still haven't fixed the bugs as of Vivado 2020.1.

Dan

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achaddha
Observer
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Registered: ‎05-13-2015

Dan,

Thanks, good to know. I am not using the ethernet-lite  core in a real project, however used it as a starting point and added the frame_write and frame_read IP. These have replaced the old VDMA IP.

Do you know if frame_write/read IP is safe to use or does it too have problems.

Arun

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