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bkamen
Explorer
Explorer
16,371 Views
Registered: ‎07-17-2014

AXI(Lite) Slave Example/Tutorial

I need some help -- I'm looking for a good coherent example/totorial for building a custom AXI-Lite Slave device in Verilog under Vivado.

This is destined to run on a MicroZed board from AvNet


The examples I've seen are either in VHDL or use the older EDK or other tools outside the Vivado suite.

I have a Wizard generated IP Device started -- but I don't know if I'm supposed to be writing my interface code at the top level or the next level down into the instantiated slave. (it looks like the maybe latter) where only my ports need to go through the top layer of the device.

This is why a good but simple example would be nice.

Thanks,

 

 -Ben

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achutha
Xilinx Employee
Xilinx Employee
16,348 Views
Registered: ‎07-01-2010

Hi,
Check this link this may help http://www.xilinx.com/support/answers/56609.html

Regards,
Achutha
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dgisselq
Scholar
Scholar
2,713 Views
Registered: ‎05-21-2015

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