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Visitor freitz85
Registered: ‎07-30-2018

AXI - UART 16550 TEMT bit in LSR register

The 16550 UART has two bits in the Line Status Register (LSR) that are changing on transmission: THRE and TEMT. The first one is set when the UART is ready to accept another character, the second one when all data has been sent. At least it should be.

I am currently working on a project that involves an RS485 connection that needs to switch the transceiver from receive to send and back. I am monitoring the TEMT bit in the LSR register to verify that all data has been sent out and that both holding and shift register are empty. However, the bit is set exactly one byte too early.  

After looking through the VHDL source in the axi_uart16550_v2_0_vh_rfs.vhd file I think I have found a problem in the TX_LOAD_SM_COM_PROCESS process. In essence, TEMT equals to signals thre_com and tsre_com. In lines 396 and following, these two signals are set as soon as the start bit is shifted out of the UART. IMHO, this is too early, because, at that moment, the shift register is certainly not empty! Instead, it should only be set when then stop bit has been shifted out.

Could you please verify this behaviour?

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