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Explorer
Explorer
310 Views
Registered: ‎10-27-2013

AXI ethernet lite MDIO status bit

Hi,

I am trying to used VHDL to control MDIO unit in Axi ethernet Lite.

While simulating I observe while initiating WRITE access , MDIOCTRL status bit has gone '0' even when phy_mdio_t remains '0' as in attached image. 

phy_mdio_t remains so for few more clock cycles.

Here If I trigger one more MDIO access , say READ,  after status bit going zero within this time gap. No MDIO access is initiated.

I was expecting that stus bit inidcated completion of MDIO access.

Please let me know the prudent mode of use MDIO interface , what delay to apply between  MDIO commands etc.

Regards

 

MDIO.jpg
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3 Replies
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Moderator
Moderator
272 Views
Registered: ‎11-09-2017

Re: AXI ethernet lite MDIO status bit

Hi

Core provides example design for reference, right click on .xci file and select open example design.

Example design contains test bench you can simulate and check MDIO interface.

Regards
Pratap

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Explorer
Explorer
266 Views
Registered: ‎10-27-2013

Re: AXI ethernet lite MDIO status bit

Hi,

 I could nit find and MDIO example. What i could find was example project where one AXI_Ethernet_lite IP communicated with another.

The traffic generator (ATG) issues done signal in 8us of simulation stating the simulation is success. There is no sufficient time to simulate MDIO transactions.

Could you please let me know how to get access to MDIO example??

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Xilinx Employee
Xilinx Employee
236 Views
Registered: ‎05-01-2013

Re: AXI ethernet lite MDIO status bit

What's the IP core you're using?

Ethernet IP should have the example in its IP core example design.

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