02-11-2020 10:48 PM
Background for this query is as follows -
Earlier in my simulations where DUT is custom Tri-speed MAC + Xilinx GMII to SGMII Bridge, and other end is SGMII VIP in the testbench, Xilinx bridge was always sending periodic data pattern 0xbc 0xb5 0x00 0x00, 0xbc 0x42 0x00 0x00 which seemed to me like bridge is attempting Auto-negotiation. As part of debug, I ran standalone simulation of the bridge and in that simulation, I saw that there is MDIO register programming being done to the bridge register (Address 0, data = 0x0080) We did the same MDIO programming in our simulation, and after that packet transmission and reception started OK between DUT and VIP.
My question is - What exactly does this MDIO programming acheive ? My guess is this disables AN and sets fixed configuration - gigabit full duplex - in this case. Is this info also transmitted to other side (testbench VIP), so that the remote partner also stops AN attempt and uses fixed configuration ?
If so, my follow-up quesion is how to simulate AN ?
Sandeep J. Sathe
02-12-2020 07:26 PM
Yes, the example always disable AN at the beginning via MDIO.
You have to enable VIP AN first to test AN. Xilinx SGMII IP can't change VIP configurations.
02-13-2020 08:45 PM
I have changed the subject name to match the subject of this question, which is about generating 25MHz and 2.5MHz clocks in 100Mbps and 10Mbps modes respectively.
I see that Xilinx SGMII to GMII bridge is generating a pulsed signal sgmii_clk_en, which is one 125MHz clock duration, and is driven every 10th clock for 100Mbps rate and every 100th clock for 10Mbps rate. Further I see that xilnx bridge drives/samples one byte data on rising edge of 125MHz clock on which sgmii_clk_en is sampled 1. (This rquires a nibble to byte and vice versa data conversion, to interface to my custom MAC which operates at 25MHz/2.5MHz nibble wide data, which by the way is as per MII spec. 12.5MHz byte wide is NOT as per MII spec, Not sure why Xilinx bridge is NOT compliant to MII standard)
ANyway, we have used MMCM which takes 125MHz output clock from Xilinx bridge and drives 125MHz, 25MHz and 10MHz div4 = 2.5MHz clocks (MMCM min output frequency is 6MHz, so we couldn't generate 2.5MHz directly from MMCM), which are muxed using BUFGMUX based on ethernet speed, and mux output is driven as a clock to our MAC.
My main question is how to align rising edge of the 25MHz clock at the MMCM output to the rising edge of 125MHz clock on which sgmii_clk_en is sampled 1 ? Can MMCM take sgmii_clk_en input signal and generate 25MHz rising edge aligned to sgmii_clk_en ?
Also, how do we generate 2.5MHz clock edge aligned ?
More I ponder over it, more I am getting inclined towards adding a small async FIFO. But my preference would be to understand how it can be done using MMCM or any other clocking resource in V7 FPGA.
Sandeep J. Sathe