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Explorer
Explorer
759 Views
Registered: ‎01-04-2013

About aurora 8b/10b back channel of timer

Hello,

part of xc6slx45t,Aurora 8b/10b v5.3 in ISE 14.6

搜狗截图20181019154635.png

Implement dataflow mode of RX-only simlex in rx-board,and TX-only simplex in tx-board.

It must have only unidirectional Fiber optic connection between rx-board and tx-board,so I must use back channel of Timer

When I Power-on the two board at the same time,the RX_CHANNEL_UP of rx-board doesn't go high during initialization.

When I Power-on the rx-board first and then Power-on the tx-board,the RX_CHANNEL_UP of rx-board can go high everytime.

Is there Power-on sequence with the IP?

Can anyone give me a example design with back channel of timer of the IP?

 

Thanks

Best Wishes.

 

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3 Replies
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Explorer
Explorer
724 Views
Registered: ‎01-04-2013

回复: About aurora 8b/10b back channel of timer

Hello?

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Xilinx Employee
Xilinx Employee
694 Views
Registered: ‎03-30-2016

Re: About aurora 8b/10b back channel of timer

Hello @danpianji88

 

Perhaps your Aurora Simplex-TX might already send out all training-sequence data (Sync & Polarity codes).

( If you power-up your RX after you TX is powered-up, or at the same time)

 

Suggest you to power-up your RX first for a workaround.

If your system needs TX to be power-up first, then you have to modify the TX timers parameter (C_ALIGNED_TIMER) to the max value, so your TX is still sending Sync & Polarity codes after your RX is powered-up.

XF_1026_A_timers.png

Thanks

Leo

 

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Contributor
Contributor
319 Views
Registered: ‎01-16-2019

Re: About aurora 8b/10b back channel of timer

I have the same qustion, I use A7 and K7 , I add a microblaze, I don't know why? 

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