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Contributor
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Registered: ‎04-10-2018

Artix 7 PCS/PMA Shared clock configuration

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Hi,

I have an Artix 7 design with two instances of the "1G/2.5G PCS/PMA or SGMII" core, and am struggling to meet timing using these in a shared clock configuration. I have one core with "Include Shared Logic in Core" set, and one with "Include Shared Logic in Example design set".

If I connect the shared logic in the most obvious way:

(instance with shared logic) -> (instance without shared logic)

gtrefclk_out -> gtrefclk

gtrefclk_bufg_out -> gtrefclk_bufg

userclk_out -> userclk

userclk2_out -> userclk2

rxuserclk_out -> rxuserclk

rxuserclk2_out -> rxuserclk2

pma_reset_out -> pma_reset

mmcm_locked_out -> mmcm_locked

gt0_pll0outclk_out -> gt0_pll0outclk

gt0_pll0outrefclk_out -> gt0_pll0outrefclk

gt0_pll1outclk_out -> gt0_pll1outclk

gt0_pll1outrefclk_out -> gt0_pll1outrefclk

gt0_pll0lock_out -> gt0_pll0lock

gt0_pll0refclklost_out -> gt0_pll0refclklost

In this configuration I cannot meet timing in the elastic buffer in the slave instance, but the master instance functions correctly.

 

I have also tried connecting the rxuserclk and rxuserclk2 inputs of the slave instance to the rxoutclk output (via a BUFH), this meets timing but the slave instance does not work.

 

I have also tried connecting the rxuserclk and rxuserclk2 inputs of the slave instance to he userclk output of the master instance, as per pg047 Figure 3-17. This is much closer to passing timing (WNS only 0.15ns, but is not an an inter clock path between userclk and userclk2), however it does not pass timing. I also tried this configuration in hardware, despite failing timing, and the slave instance did not work.

 

Does anybody know the correct clock configuration for this mode of operation? Is there a working example available? The FPGA is largely empty other than these MIG instances. The GT lanes are on the same Quad. I am currently using Vivado 2018.2.

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Contributor
Contributor
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Registered: ‎04-10-2018

It turns out that I had make a mistake in the configuration of the MAC in the slave instance, which was causing my problems, the PCS/PMA was working correctly in a configuration where rxoutclk comes from the local instance.

For anyone interested in the future the "correct" solution (as in the only solution that both meets timing and works for me) is to, on the slave instance, connect rxoutclk to a BUFH, then connect the output of this BUFH to the rxuserclk and rxuserclk2 ports. All other shared logic signals should be passed through directly from the master.

This configuration seems to work for me with simple testing, I'll post back if I have any further issues.

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Contributor
Contributor
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Registered: ‎04-10-2018

It turns out that I had make a mistake in the configuration of the MAC in the slave instance, which was causing my problems, the PCS/PMA was working correctly in a configuration where rxoutclk comes from the local instance.

For anyone interested in the future the "correct" solution (as in the only solution that both meets timing and works for me) is to, on the slave instance, connect rxoutclk to a BUFH, then connect the output of this BUFH to the rxuserclk and rxuserclk2 ports. All other shared logic signals should be passed through directly from the master.

This configuration seems to work for me with simple testing, I'll post back if I have any further issues.

View solution in original post

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