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Explorer
Explorer
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Registered: ‎11-03-2013

Artix7 SGMII RX clock connection

In the documentation, regarding the clock connections for SGMII in Artix7 FPGA, it looks like the "rxuserclk" and "rxuserclk2" are connected to the same wire as the "txuserclk" and "txuserclk2" (figure 3-10).

But in the example design for the SGMII I see that the "rxuserclk" and "rxuserclk2" are connected to the "rxoutclk" (via BUFG).

What is the correct connection?

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exmaple_dsn.png
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Moderator
Moderator
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Registered: ‎11-09-2017

Hi @goychman

Figure 3-10 refer to 1000 base-x so rxuserclk" and "rxuserclk2" are connected to the same wire as the "txuserclk" and "txuserclk2".

Please refer to figure 3-14  if you are looking for SGMII "rxuserclk" and "rxuserclk2" are connected to the "rxoutclk" (via BUFG).

Regards
Pratap

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