UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
342 Views
Registered: ‎11-03-2013

Artix7 SGMII RX clock connection

In the documentation, regarding the clock connections for SGMII in Artix7 FPGA, it looks like the "rxuserclk" and "rxuserclk2" are connected to the same wire as the "txuserclk" and "txuserclk2" (figure 3-10).

But in the example design for the SGMII I see that the "rxuserclk" and "rxuserclk2" are connected to the "rxoutclk" (via BUFG).

What is the correct connection?

docs.png
exmaple_dsn.png
0 Kudos
1 Reply
Moderator
Moderator
252 Views
Registered: ‎11-09-2017

Re: Artix7 SGMII RX clock connection

Hi @goychman

Figure 3-10 refer to 1000 base-x so rxuserclk" and "rxuserclk2" are connected to the same wire as the "txuserclk" and "txuserclk2".

Please refer to figure 3-14  if you are looking for SGMII "rxuserclk" and "rxuserclk2" are connected to the "rxoutclk" (via BUFG).

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
0 Kudos