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jordanki_brc
Visitor
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Registered: ‎10-19-2011

Aurora 64B/66B Received Data Doubled|Tripled

I have been working with the Aurora 64B/66B core (v6.1, ISE 13.2, VHDL, streaming simplex Tx and Rx, 4 lanes) with two V6 LX240T on separate PCBs (ref clk 312.5 MHz +/- 20ppm, data rate at 6.25 Gbps).  The issue I am observing is that sometimes after a clock correction sequence, the next data word to appear valid from the Aurora core is repeated for an additional cycle with indications that the data is valid (on rarer occasions I observe data repetition more than one additional cycle, but not more than three additional).  I am assuming that a clock correction is what is happening on the Rx side due to the long pause just prior to the issue appearing, and the only place I observe such a pause in simulation is after a clock correction sequence arrives at the Rx endpoint.  Currently, I am using the LFSR data generator supplied with the example design on the Tx side, and the LFSR sequence checker on the Rx side.  When this issue occurs, the Rx sequence checker becomes out of sync with the incoming data and thus all received data is flagged as erroneous.

 

I have created a work around that pauses data transmission for two additional cycles on the Tx side after a clock correction sequence is sent.  This prevents the issue from appearing as frequently (takes several minutes for issue to appear instead of within first few clock correction periods), however, this fix is not desired as I need as much bandwidth as possible in my application.  I have included a capture from ChipScope where the sequence became out of sync after a data word was fed to the sequence check twice by the Aurora core.  The lengthy pause prior is where I assume a clock correction occurs.

 

AURORA_ERROR.png

 

I have used ChipScope on the Tx side to monitor for a double push of a data word, but have not observed such an occurrence.  I will also note that I did not see any occurance of this issue when I was testing locally on the same PCB.  Any suggestions or questions are appreciated!

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mbarber
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Registered: ‎09-13-2007

From what I understand this problem has been in the 64B/66B core since it's release, Xilinx has not corrected (or even addressed it) it yet through 13.3 release even thought webcases had been created!

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toshas
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Registered: ‎02-14-2009

I am using ml605 (sma loopback) with ISE13.2, aurora_core 64b66b v5.1 and v6.1.

 

Example design ver5.1 works fine but ver6.1 generates Data_errors (I can see it on leds, via chipscope, and even in isim at ~2.5ms).

 

There are two majour differences after comparison source files:

 

1. in channel bonding clock sequence (cb_cc) and gtx_wrapper was added line_reset mechanism if there is no CC more than 10000 cycles.

AR Hot Plug - http://www.xilinx.com/support/answers/39645.htm

 

2. tx_ll_control_sm changes not documented so well as first thing.

 

line 363 - ("!datavalid_in_r" used in v5.1 and commented in 6.1)

// else tx_dst_rdy_n_r <= `DLY tx_dst_rdy_n_c |!TXDATAVALID_IN |!datavalid_in_r ;

   else tx_dst_rdy_n_r <= `DLY tx_dst_rdy_n_c |!TXDATAVALID_IN; 

 

line 380 - in v6.1 added new delay

// Additional states to latch GEN_SEP when datavalid & CC coincides

       else if (gen_sep_r & gen_sep_nb_r == {1{3'h0}} & GEN_CC) 

             GEN_SEP <= `DLY gen_sep_r; 

 

After bringing back changes in tx_ll_control_sm file example design ver6.1 seems to be work.

 

Still waiting answer from xilinx about this webcase!

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jordanki_brc
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Registered: ‎10-19-2011

toshas:

 

   I don't think our problems are related, but I will investigate further.  The reasons why I don't think they're related are:

  • I'm using the VHDL AXI Streaming Tx and Rx only implementation and I can see you are using one of the Verilog implementations.  I have seen that the various implementations are mostly the same, but differences between the implementations (AXI vs. LocalLink, Streaming vs. Framing, VHDL vs. Verilog, Duplex vs. Simplex) exist.  For example, I don't see a file in my sources that corresponds to your tx_ll_control_sm file.
  • The design I'm working with bonds and operates, but after a clock correction has occured, the transmitted data is seen by the receive side multiple times.  This causes my data errors because the sequence is off from that point forward.

The answer note you mentioned appears to be implemented in my sources (very bottom of my Rx channel (your instance name)_wrapper.vhd file.

 

If you could post an image of the iSim sequence, I would like to see if it is similar behavior that I am encountering.  Unfortunately, I haven't been able to reproduce the issue I have encountered in a simulation.  It may be that I'm not running a simulation long enough, but I have tried to run for several milliseconds and still did not see it occur.

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toshas
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Registered: ‎02-14-2009

Yesterday i saw that ISE 13.4 became avaible.

There is also aurora 64b66b update 6.2.

Release notes located here http://www.xilinx.com/support/answers/45671.htm .

 

"Resolved Issues

1. Virtex-6QL devices are not supported Description: Core is not enabled when Virtex-6QL devices are selected

2. Unroutable Placement on BUFDS/GT clock component pair Description: 7 series FPGA designs error out due to unroutable BUFDS/GT pair

3. Data Frame missing on RX side Description: Missing one data frame on receive side

4. BitGen errors for 7 series FPGA designs Description: BitGen errors for 7 series FPGA designs"

 

It seems like point 3 is about our problem. I will check tommorow.

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