12-31-2014 02:04 PM
I'm using Vivado 2014.1 and I generated
1) Aurora 64b/66b example design (V9.2) 
2) 7 series FPGAs Transceiver Wizard example design (V3.2) follwing the instructions in Appendix D of 
for xc7k325tffg900-2. I measure the latency on a Kintek7 FPGA in NE PMA loopback, where the latency * is defined as the difference in user_clk cycles between the same packet in tx and rx, as seen in ila. I obtain
1) ~ 50 clks
2) ~ 30 clks
Why such a large difference? By looking a Fig 2.2 of  and at the F/Ws in 1) and 2) I can guess that the AXI4-stream+PE add a consistent amount of user_clk cycles because it has to deal with asynchrounous clks, as described in . Am I mistaken?
If my guess is correct, I'd like to ask you
Last but not least, notice that a similar behavior (but relatively smaller difference) is seen in Aurora 8b/10b, where I get
1) 38 ckls
2) 31 clks
Thanks a lot
*: I also estimated the latency according to definition in  (difference in user_clk cycles between
the first assertion on s_axi_tx_tvalid and s_axi_tx_tready to m_axi_rx_tvalid): I obtain about 46 clks, which is somehow consistent with  (slightly smaller because of the different loopback mode, I guess)
01-05-2015 02:42 AM
01-05-2015 05:59 PM
You cannot compare GT wizard design with Aurora. With Aurora IP, it has protocol implemented in data path along with transceiver interface.
Along with latency, compare the number of GT blocks used by 8B10B and 64B66B cores.
Thanks for your answer: I understand now why the Aurora 64b/66b example design has a larger latency wrt the gt wizard example design. I also understand why such a difference is not as large in the 8b/10b case
With 8B10B, most of the required blocks are available from GT but with 64B66B some functionality of the protocol is needed to be implemented in fabric.
Concerning the last part of your answer I still have some doubts. The GT wizard design works properly when sending packet from one FPGA to another: doesn't this mean that it works fine in fabric?
One more question: is the extra logic of the Aurora example design targetting only the clock compensation? Or is there something else?
01-06-2015 10:20 AM