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905 Views
Registered: ‎06-30-2017

Aurora 8B10B v11.1 - multi instance design fails in simulation during elaboration stage

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Hello, 

 

I have the task to design a multi instance aurora communication IP, where the user can choose via generics how many instances he will use. 

 

On our PCB the lanes 4,5,6,7 and 13,14 are connected to transceivers, thus we are forced to use this lanes. 

 

We will use the Aurora 8B10B v11.1 form Vivado 2018.2.

 

Due to the fact I can not configure a Xilinx IP core via generics in VHDL, I choose the following approach to generate a IP core with variable number of interfaces:

  - generate a block design with all user logic and the aurora core (including shard logic in core)

  - customize the aurora core for lane 4.

  - package Bd to a IP core

  - customize the aurora core for lane 13

  - package Bd to a IP core 

  - generate a block design with all user logic and the aurora core (include Shared Logic in ecample design)

  - customize the aurora core for lane 5, 6, 7, 14

  - package Bd to Ip core (lane 5,6,7,14)

 

Now I have 6 IP cores. Two of them have the shared logic included in the IP core, four have the shared logic included in example design. This is necessary because there is a quad in between the used quads (quad 2 & 4)

 

Next Step is to generate a top level vhdl file, where I instantiate the ip cores depending on the specified number of instances. 

eg. if NoOfInst=3, lane 4, lane 5, lane 6 are instantiated. Lane 4 includes the shared logic and shares it with lane 5,6. 

When NoOfInst is greater 4, lane 13 is instantiated and includes the shared logic which will be shared with lane 14. 

 

This works fine als long NoOfInst<=4, thus as long all ip cores include the aurora block configured to use the lanes from the same quad. 

 

When NoOfInst>4 then the simulation fails with the following error code:

 

Starting static elaboration
ERROR: [VRFC 10-718] formal port <gt_qpllclk_quad4_out> does not exist in entity <mgr_sl>.  Please compare the definition of block <mgr_sl> to its component declaration and its instantion to detect the mismatch. [C:/viv2018.2/ip_repo/MGR/MGR_TOP/OpCom.srcs/sources_1/ip/mgr13_0/sim/mgr13_0.vhd:102]
ERROR: [VRFC 10-718] formal port <gt_qpllrefclk_quad4_out> does not exist in entity <mgr_sl>.  Please compare the definition of block <mgr_sl> to its component declaration and its instantion to detect the mismatch. [C:/viv2018.2/ip_repo/MGR/MGR_TOP/OpCom.srcs/sources_1/ip/mgr13_0/sim/mgr13_0.vhd:103]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

When I check the files everything seams ok for me. I attached the following files:

 

C:/viv2018.2/ip_repo/MGR/MGR_TOP/OpCom.srcs/sources_1/ip/mgr13_0/sim/mgr13_0.vhd

C:/viv2018.2/ip_repo/MGR/MGR_TOP/OpCom.srcs/sources_1/ip/mgr13_0/sim/mgr_sl.vhd

 

It seams that there is a problem with the shared logic. Or do I overlook something? 

 

Regards, Stephan 

  

 

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467 Views
Registered: ‎06-30-2017

Re: Aurora 8B10B v11.1 - multi instance design fails in simulation during elaboration stage

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I found the problem! As described in my initial post I used two BD as template. From them I derived the IP cores for different lanes.

 


@stephan_hochmueller wrote:

 

  - generate a block design with all user logic and the aurora core (including shard logic in core)

  - customize the aurora core for lane 4.

  - package Bd to a IP core

  - customize the aurora core for lane 13

  - package Bd to a IP core 

  - generate a block design with all user logic and the aurora core (include Shared Logic in ecample design)

  - customize the aurora core for lane 5, 6, 7, 14

  - package Bd to Ip core (lane 5,6,7,14)

 

 


Generating a IP core with the same block design results in a top level vhdl file which has the same name but different configuration. I created a separate block design for each lane. Now each top level file has a different name and the code is synthesis-able.  


 

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Registered: ‎06-30-2017

Re: Aurora 8B10B v11.1 - multi instance design fails in simulation during elaboration stage

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Hello, 

 

I tried to synthesis the Ip Core now. I hoped that when I use just the 4 instances in synthesis I can test the design like I did in simulation were this was working. But it results in the same error as described in the last post. I was checking the source files. The component declaration and instantiation is consistent. But the tool disagrees. I attached the error message. 

 

I have the feeling Vivado is somehow changing the design of the aurora block. Is it possible that Vivado displaces the shared logic settings? 

 

Regards,

Stephan 

mgrError.PNG
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735 Views
Registered: ‎06-30-2017

Re: Aurora 8B10B v11.1 - multi instance design fails in simulation during elaboration stage

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Hello,

 

in the following image you can see how my ip structure is. Each arrow is a instantiation, each block is a packaged ip core (except the sytem_top which is the top level design. ip structure 

 

I figured out now that I can synthesize the mgr_top_ip_proj. But as soon I instantiate it in the top level project synthesis of this block fails. (I packaged the mgr_top_ip_proj). 

 

It can't be a design error due to the fact that mgr_top_ip_proj is synthesis-able. 

 

Is it possible that I do something wrong while I package the ip? 

 

thank you,

Regards, Stephan

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729 Views
Registered: ‎06-30-2017

Re: Aurora 8B10B v11.1 - multi instance design fails in simulation during elaboration stage

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but in mgr_top_ip_proj the problem with the simulation of the initial post exists. 

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468 Views
Registered: ‎06-30-2017

Re: Aurora 8B10B v11.1 - multi instance design fails in simulation during elaboration stage

Jump to solution

I found the problem! As described in my initial post I used two BD as template. From them I derived the IP cores for different lanes.

 


@stephan_hochmueller wrote:

 

  - generate a block design with all user logic and the aurora core (including shard logic in core)

  - customize the aurora core for lane 4.

  - package Bd to a IP core

  - customize the aurora core for lane 13

  - package Bd to a IP core 

  - generate a block design with all user logic and the aurora core (include Shared Logic in ecample design)

  - customize the aurora core for lane 5, 6, 7, 14

  - package Bd to Ip core (lane 5,6,7,14)

 

 


Generating a IP core with the same block design results in a top level vhdl file which has the same name but different configuration. I created a separate block design for each lane. Now each top level file has a different name and the code is synthesis-able.  


 

0 Kudos