07-24-2017 10:20 AM
I am using Aurora 8b/10b v11.0 with Vidado 2016.2 in a loopback mode at 3.125Gbps. The loopback is done through SFP+ transcievers are plugged on a board from Faster-Technology, named FM-S14-C (http://www.fastertechnology.com/products/fmc/fm-s14.html) I use dual-lane aurora and SFP+ transcievers that are connected to aurora are placed at GTXE2_CHANNEL_X0Y12 and GTXE2_CHANNEL_X0Y13.
I miss the first word of each package, well it may not be counted as a data loss, because when I observed from the debugger, I see that the data is exactly where it should be, but the data_valid signal(m_axi_rx_tvalid) is not there for that clock cycle. When I further examined the data_valid behaviour I have not encountered any sign of latency, the data valid signal is not late but missing. As seen below, the 0x0001 should be valid for 3 cycles, but first cycle of valid is not there.
Various diagnostic information for your convenience when answering:
- I tested my SFP+ transcievers with IBERT. No erroneous condition occurred.
- I tested and encountered same problem with a lower data-rate(2Gbps).
- I have encountered the same problem with different SFP+ transcievers.
- I have encountered the same problem with different optical cables.
- I even tried with another(brand new) KC705 board and still got the same result.
- Most importantly, I tested the same system with a loopback at
PCI-E port(GTXE2_CHANNEL_X0Y4 and GTXE2_CHANNEL_X0Y7) and did not encounter the problem, this problem only occurs when I connect the aurora peripherals to SFP+ connectors.
Various reasoning I have conducted for your convenience when answering:
- The length of data package is not the problem since the erroneous condition occurs at the receiving end way before the end of package.
- Timing might be a problem but lowering the data rate had no effect and the design meets all timing constraints so it is close to the end of the list.
Thank you for your attention.