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Registered: ‎08-10-2016

Aurora 8b10b multi-lane data misalignment

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Hello all,

 

I am trying to test the MGT banks in Artix-7 (XC7A200TFBG676-2) FPGA on a custom board. The line rate is 0.5 Gbps with a reference clock of 125MHz supplied by an external clock source. I am using a single Aurora 8b10b IP core in Full Duplex mode with 4 lanes and 2 bytes per lane.

I am testing the design with a physical loop back. I write, say 16 bytes, to the AXIS TX interface and then read out the AXIS RX interface and compare the 2 buffers.

The MGT_216 bank works perfectly with this setup. I could even increase the line rate to 6.25 Gbps and still it works. However, when testing the same design with the MGT_213 bank with 0.5 Gbps, lanes 0 and 2 work fine, however, I observe a data skew in lanes 1 and 3. During the first beat, I get the data expected in the second beat. The output consists of IDLE and END OF FRAME characters for the second beat.

 

Comparison

Comparison.PNG

 

More info:
1. Channel_UP is always HIGH
  In a multi-lane design, this happens only after the lanes are synchronized. Right?

2. All 4 lane_UP are HIGH
  This means initialization is done and stable. Right?

3. No Hard, soft or frame errors

The data skew appears in the RX AXIS interface itself. When TLAST is asserted, the TKEEP signal is 0xC0, meaning I have to ignore the last 6 bytes.

 

 

TX Image:

 

TX.PNG

 

RX Image:

 

RX.PNG


Where are those bytes? Why does that happen and how can I solve it? Any pointers are appreciated.

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1,327 Views
Registered: ‎08-10-2016

Re: Aurora 8b10b multi-lane data misalignment

Jump to solution

I solved this problem, only partially though.

The problem is that the connector I am using in my hardware, to do the loopback test, interchanges the lane connections and completely jumbles it up. For ex., after a loopback, MGT_213_TXN0 is connected to MGT_213_RXN3 and so on. When Aurora core (or any other core instantiating the GTP transceivers for that matter) is configured in duplex mode, one cannot change the pin assignments in the constraints file. This is because the location of RXP, TXN and TXP pins of a particular GTP is automatically mapped when one specifies the location for RXN pin, and vice versa. As far as I understood, in a multi-lane design, one of the GTPs is configured as a Master and the other three as Slaves. This plays a vital role in data alignment somehow. When the loopback messes this up, then alignment is also messed up and data is lost. I am not sure here, someone can explain this perhaps.??

Solution (partial), finally!
I used 2 Aurora Simplex cores, Bank_213 for TX and Bank_216 for RX (also vice versa) and changed the pin assignments in constraints file so that after loopback, MGT_213_TXN0 goes into MGT_216_RXN0. This time the constraints were valid. As per my understanding, this time it is possible to change the pin assignments because the GTPs in that particular bank are either TX or RX and never both at the same time. For ex., can change the locations of TX pins independent of the RX because they never lie in the same bank.

This is only a partial solution, because I have to load the FPGA design twice in order to verify all the GTP pins for functionality. This suffices my requirement.

View solution in original post

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1,033 Views
Registered: ‎08-10-2016

Re: Aurora 8b10b multi-lane data misalignment

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Since the MGT_216 was working well, I tried to send the data from the TX lanes in the TOP MGT (216) and receive them in the bottom MGT (213), both configured as Simplex Aurora IPs. This worked. No skew in data. So the problem is not on RX side of the MGT_213.

 

However, when I tried the reverse setup, i.e., MGT_213_TX to MGT_216_RX, then there seems to the same problem. I loose 3 data beats for the first cycle.The data corresponding to the second cycle appears in the first cycle. For the second cycle, I am reading EOP and IDLE characters.

 

This has led me to believe that there is some problem in the MGT_213_TX lanes. Maybe in hardware.

 

What all should I check? Could anyone help.?

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Highlighted
1,328 Views
Registered: ‎08-10-2016

Re: Aurora 8b10b multi-lane data misalignment

Jump to solution

I solved this problem, only partially though.

The problem is that the connector I am using in my hardware, to do the loopback test, interchanges the lane connections and completely jumbles it up. For ex., after a loopback, MGT_213_TXN0 is connected to MGT_213_RXN3 and so on. When Aurora core (or any other core instantiating the GTP transceivers for that matter) is configured in duplex mode, one cannot change the pin assignments in the constraints file. This is because the location of RXP, TXN and TXP pins of a particular GTP is automatically mapped when one specifies the location for RXN pin, and vice versa. As far as I understood, in a multi-lane design, one of the GTPs is configured as a Master and the other three as Slaves. This plays a vital role in data alignment somehow. When the loopback messes this up, then alignment is also messed up and data is lost. I am not sure here, someone can explain this perhaps.??

Solution (partial), finally!
I used 2 Aurora Simplex cores, Bank_213 for TX and Bank_216 for RX (also vice versa) and changed the pin assignments in constraints file so that after loopback, MGT_213_TXN0 goes into MGT_216_RXN0. This time the constraints were valid. As per my understanding, this time it is possible to change the pin assignments because the GTPs in that particular bank are either TX or RX and never both at the same time. For ex., can change the locations of TX pins independent of the RX because they never lie in the same bank.

This is only a partial solution, because I have to load the FPGA design twice in order to verify all the GTP pins for functionality. This suffices my requirement.

View solution in original post