07-18-2019 04:22 PM
I don't care about hot-swapping and I have boards that have a shared clock that is both phase and frequency locked.
How do I disable the clock compensation logic for my case?
07-23-2019 12:32 PM
I have the tx/rx simplex example design for Aurora running on a KCU105 in a loopback.
The link goes down for ~600 cycles every so often - we can't go down that long, it is A) too much latency and B) would massively increase the amount of buffering we need to do.
I thought the link doing that was due to clock compensation, so I'd like to disable it or minimize it as much as possible.
07-24-2019 10:04 AM
It looks to me like tready is going down while channel bonding and/or clock compensation occurs - if this goes down, I'm unable to hand data to the core, so I have to buffer it externally.
The ~600 cycles I'm seeing are from channel bonding, and during that time it looks like tready is low, so I'd have to buffer a tremendous amount of data.
The cores are simplex - we do not have a back-channel, so the simplex TX core periodically asserts channel bonding. The best I think I can do (without going full duplex) is to feed back the "rx lane up" to the tx simplex core (1 line) so as to prevent recurring channel bonding (unless there's an error, of course).
So basically I'd need to control channel bonding in the case of a simplex design, in order for the core to continually accept data, unless there's something else I don't understand.