cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
4,523 Views
Registered: ‎05-03-2008

Aurora RocketIO Clocking Problems

Jump to solution

I am using Aurora with a  Virtex5 FPGA. The MGT tile i need to use is not connected to an external clock. So i have to rout the clock from another MGT tile as far as i found out in the user guide. I am not able to rout the clock.

 

I did the following:

1- Generated the Aurora with the MGT i need

2- Made another instance of the MGT with the external clock. Only the MGT. I set most inputs to 0 and outputs to open.

3- Made instances of all the MGTs between the one i need and the one with the clock

4- used the same CLKIN for all MGTs.

 

This is not working. The MGT with Aurora is not initializing and not generating a user clock. Only the MGT with the external clock is working. This leads me to conclude that the routing of the clock is not working.

 

Could anyone please give me some hints on how this routing has to be done?

Thanks

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
4,764 Views
Registered: ‎05-03-2008

Thanks for the hints. Actually i found that the problem is the following:

 

I made intances of the RocketIO tranceivers through which the clock is passing. The instances could be found in the synthesis schematics but not in the FPGA editor (after mapping). I had to connect the IO pins (RXD,TXD) of the unused MGTs to signals on the top level module to get them really mapped.

 

When i did this things worked smoothly!

View solution in original post

0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
4,516 Views
Registered: ‎01-03-2008

I would start by checking the design in FPGA Editor to verify that the reference clock is correctly connected to the MGT that isn't working.

 

If it looks correct then I would connect the REFCLKOUT pin of the failing MGT to a pin to verify that it is toggling.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
Highlighted
Anonymous
Not applicable
4,504 Views

Also make sure that of the MGTs in between the signal REFCLKPWRDNB is set to '1'. If it is '0', the clock routing will be powered down.

The REFCLK can only move up or down 3 tiles from the tile it comes in on.

Highlighted
Observer
Observer
4,765 Views
Registered: ‎05-03-2008

Thanks for the hints. Actually i found that the problem is the following:

 

I made intances of the RocketIO tranceivers through which the clock is passing. The instances could be found in the synthesis schematics but not in the FPGA editor (after mapping). I had to connect the IO pins (RXD,TXD) of the unused MGTs to signals on the top level module to get them really mapped.

 

When i did this things worked smoothly!

View solution in original post

0 Kudos