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Contributor
Contributor
6,628 Views
Registered: ‎03-12-2008

Aurora Simplex CC_Module IO Port misnaming issue...

So I was reading through the standard cc module for a 4 lane simplex tx aurora core v3.0 today.

I noticed that the comments mention monitoring the channel up signal.  Then I started reading the user guide ug353.  It lists the standard cc io ports as...

WARN_CC, DO_CC, and CHANNEL_UP.

Guess what is not in the module that coregen gave me...  That's right CHANNEL_UP.  There is a RESET port.  And it seems to be used in the CC module in places where it refers to CHANNEL_UP.  But I can't really tell if I need to connect a CHANNEL_NOT_UP or CHANNEL_UP to the RESET port.

So I looked at the example code that coregen provided... That's right CHANNEL_UP is not connected to the CC_MODULE in the example.

 

Anyone resolved this issue already?

 

Thoughts?

 

Message Edited by saikey on 08-04-2008 07:13 PM
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2 Replies
Contributor
Contributor
6,612 Views
Registered: ‎03-12-2008

Re: Aurora Simplex Clock Correction Module

So I connected ~TX_CHANNEL_UP to the reset of the CC_MODULE.

It works much better now.  I am still not entirely convinced that this is the complete solution based on the code in the CC_MODULE, so I will open a web case to make sure.  I'll re-post the answer next week when I get it (haha).

 

-Shawn

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Contributor
Contributor
6,590 Views
Registered: ‎03-12-2008

Re: Aurora Simplex Clock Correction Module

Faster than expected response...  But I am always prepared for disapointment from web support of any kind.

Basically seemed to indicate that ~CHANNEL_UP should be connected to the reset port of the CC_MODULE.  Although the exact response was not exactly in complete sentences.

<QUOTE>

This is a bug which is due to some fix we made recently. It will be fixed in the future release It’s is better to connect CHANNEL_UP and TX_CHANNEL_UP or inverted RESET as this happens

 

 If clock module is continuously kept in RESET (and RESET is active low in example design).

</QUOTE>

 

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