08-25-2017 01:37 AM
We have 2 PCBs, each equipped with a XC7A35TCPG236-2C FPGA.
They communicate using their transceivers and an aurora core with a line rate of 1Gbps. The transceiver reference clocks are independent differential 125MHz clocks.
This works fine, the channel comes up and remains so.
We now have a new PCB, equipped with an XC7A50TCPG236-1C FPGA (i.e. more logic and "worse" speed grade) and otherwise identical setup, apart from some pin changes and whatnot, but the transceiver configuration as well as the source VHDL remained identical. When connecting this new board with an older board (with an XC7A35TCPG236-2C), we see the channel_up being asserted for short periods, but it's not stable.
If we now pass the clock from the new PCB to the older PCB and use it on the older one as the GTP reference clock, the channel does come up and stays up.
We have looked in every corner and have not come up with a solution that works with two independent clocks.
Is it possible this issue is due to the different FPGA / speed grade?
Any other clue why this would occur?
08-26-2017 06:33 AM
have you cross checked the specs, the lowest speed the link can run at ?
1 Gb/s seems a little slow.
check the clocks PPM, I've had a few duff oscillators in the past, well outside their expected PPM. can you swap the oscilators over see if the fault follows them.
Have you checked the eye diagram, see how 'good' the link quality is,
Have you seen this ?
gives a few good hints to follow at this stage
08-27-2017 11:29 PM
You can do IBERT test first to make sure that the link quality is good.
And do new board near end loopback test as well, both GT internal PMA near end loopback and cable outside near end loopback (TX => RX).