UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,885 Views
Registered: ‎08-25-2017

Aurora channel only stable with common GTP clock

We have 2 PCBs, each equipped with a XC7A35TCPG236-2C FPGA.

 

They communicate using their transceivers and an aurora core with a line rate of 1Gbps. The transceiver reference clocks are independent differential 125MHz clocks.

 

This works fine, the channel comes up and remains so.

 

We now have a new PCB, equipped with an XC7A50TCPG236-1C FPGA (i.e. more logic and "worse" speed grade) and otherwise identical setup, apart from some pin changes and whatnot, but the transceiver configuration as well as the source VHDL remained identical. When connecting this new board with an older board (with an XC7A35TCPG236-2C), we see the channel_up being asserted for short periods, but it's not stable.

 

If we now pass the clock from the new PCB to the older PCB and use it on the older one as the GTP reference clock, the channel does come up and stays up.

 

We have looked in every corner and have not come up with a solution that works with two independent clocks.

 

Is it possible this issue is due to the different FPGA / speed grade?

 

Any other clue why this would occur?

 

 

Thanks

 

Jasper

0 Kudos
2 Replies
Scholar drjohnsmith
Scholar
1,835 Views
Registered: ‎07-09-2009

Re: Aurora channel only stable with common GTP clock

have you cross checked the specs, the lowest speed the link can run at ?

   1 Gb/s seems a little slow.

 

check the clocks PPM, I've had a few duff oscillators in the past, well outside their expected PPM. can you swap the oscilators over see if the fault follows them.

 

Have you checked the eye diagram, see how 'good' the link quality is,

     

Have you seen this ?

 

https://www.xilinx.com/support/answers/57237.html

 

gives a few good hints to follow at this stage

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Xilinx Employee
Xilinx Employee
1,779 Views
Registered: ‎05-01-2013

Re: Aurora channel only stable with common GTP clock

You can do IBERT test first to make sure that the link quality is good.

And do new board near end loopback test as well, both GT internal PMA near end loopback and cable outside near end loopback (TX => RX).

0 Kudos