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Contributor
Contributor
12,089 Views
Registered: ‎07-09-2012

Aurora loopback between two transceivers in the same tile ML507

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Hi,

 

I am trying to implement an Aurora link between the two transceivers in the X0Y3 tile of the ML507 (XC5VFX70T) board. I am trying to complete a loopback test over a SATA link. How many Aurora cores would I need to generate? My understanding is that each Aurora lane/channel uses one transceiver so I would be needing two separate Aurora cores. I am not sure how i would combine them in a single project. Any help is appreciated.

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Moderator
Moderator
17,646 Views
Registered: ‎02-16-2010
Yes. You will need to re-label signals of the individual cores on the top level and connect them at that level
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Community Manager
Community Manager
12,081 Views
Registered: ‎07-23-2012
If you are planning to have the same line rate and ref clk frequency for both the tiles, then you can generate a single aurora core with two lanes.
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2012

The following AR http://www.xilinx.com/support/answers/21263.htm also having useful knowledge related to your query

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Moderator
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Registered: ‎02-16-2010
refer to Appendix A of ug353
http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b/v5_3/aurora_8b10b_ug353.pdf
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Contributor
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Registered: ‎07-09-2012

The issue here is that both transceivers are in the same tile so i can't just generate a core with 2 lanes.

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Community Manager
Community Manager
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Registered: ‎07-23-2012
You need to generate two cores and stitch them together (by manually editing) to make use of single dual tile.

Refer to the link provided by @venkata.
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Contributor
Contributor
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Registered: ‎07-09-2012

I have looked into that portion of the UG but I am not sure about how to implement the stiching of the two cores in one project. Do i have to re-label signals of the individual cores on the top level and connect them at that level? Any previous work that i can take pointers from?

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Moderator
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Registered: ‎02-16-2010
Yes. You will need to re-label signals of the individual cores on the top level and connect them at that level
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Observer
Observer
10,583 Views
Registered: ‎05-14-2014
hi,
I am doing the same thing with PCIE protocol. How can I write the UCF file for loop back testing and is there any jumper setting for loop back ?
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Moderator
Moderator
10,580 Views
Registered: ‎02-16-2010
can you create a different post in PCIe board?
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Observer
Observer
7,266 Views
Registered: ‎05-14-2014

Hi, 

 

My problem is wtih GTX & SATA . Anyways give me thread of PCIE 

 

Thanks

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Moderator
Moderator
7,261 Views
Registered: ‎02-16-2010
In the previous post you mentioned about PCIe. This is why I have told to create topic in PCIe board.

If it is between GTX and SATA, then create a new topic in this board itself.
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