07-01-2008 05:24 AM
Hello. I have a problem using Xilinx's protocol Aurora.
The design on my v4fx board is : aurora v2.8, native flow control, 2.5Gbps, 125 Mhz ref clock.
In parallel loopback mode, both lane_up and channel_up switch in high and low state. The result is that the communication is interrupted (with hard and soft errors indications).
In serial loopback mode, both lane_up and channel_up stay in low state.
Can anyone help me with this problem?
07-01-2008 02:04 PM
The only way to get Native Flow Control is with a duplex link. Your not looping the transmit side of your link back to its' own receiver are you? Because that receiver is expecting some signalling from the channel partner for status information, etc... You need to have two seperate Aurora cores instantiated and connect them to each other.
07-01-2008 03:34 PM
Thanks for your response,
the problem is that the loopback mode is a looping in the same Aurora core (105a in my case).
Is it possible to test only 1 (one) Aurora core with loopback mode ?
But my main problem is that the line_up and channel_up are unstabe (high and low states switching) in operational mode (aurora link between 2 v4fx boards). The same behavior (line_up and channel_up unstabe) is noticed in the parallel loopback mode, it's why I want to work the loopback mode above all.
Thanks if you have any suggestions
07-10-2008 10:01 AM
I think that loopback should work, contrary to what pp said.
Are you getting RXNOTINTABLE toggling? How about RXREALIGN?
01-12-2009 05:02 PM
01-15-2009 09:22 AM
02-13-2009 12:38 PM
i have the same problem in Virtex 5 lx220t, exept the togling of channel_UP and Lane_UP (they don't rise), i see toggling of DISPERR , NOTINTABLE, may be you have resolved this problemm and have some suggestions
05-14-2009 01:46 PM
Anymore finding on this issue?
I have Virtex 4 FX20 communicating to Virtex II Pro 4.
Both ends occasionally get lane_up dropped then recovered.
05-21-2009 01:05 AM
I have the same question1
i use aurora3.0 between v5 and pro20 FPGA!
In my programme, channel_up and lane_up is not constant HIGH, sometimes is LOW!
can you solve the question?
07-24-2009 09:35 AM
07-27-2009 09:41 AM
I've had problems with V4 MGT links as well. I occasionally have an MGT link fail to initialize or drop out. In analyzing these occasional failures, I've been looking more closely at the GT11_INIT modules generated with the core to provide reset/initialization sequencing. From the documentation inthe MGT user's guide, the RX reset SM monitors RXBUFERR, RXDISPERR, and RXNOTINTABLE and performs a PCS reset if any of these signals are asserted. However, in the example design provided with the core, only RXBUFERR is monitored (RXBUFERR drives the PCS_ERROR signal into the RX GT11_init module). I'm unclear how RXDISPERR and RXNOTINTABLE should be used.