05-21-2014 09:07 AM
We are using Aurora simplex timer based streaming mode in our design.Aurora simplex-TX of one board is connected to Aurora simplex-RX of other board.We generated Aurora Simplex-TX and Aurora Simplex-RX core from core generator (Auora8b/10B V8.3) and generated bit files with examples design.
we programmed bit and started testing,observed that aurora RX-Laneup is not at all coming up.
After that we generated bit files with aurora duplex to check connectivity between boards,its working fine.But with simplex bit files ,we are not seeing any lane up and also didnt find any alignement sequence( i.e BC4A 4A4A BC4A4A).But we are seeing lane intialization( i.e BC4A 4A4A BC4A4A) pattern at the transmitter side.
1)we are using defualt timers at transmitter side (C_ALIGNED time 6143 and C_VERFIED timer 8191)
2)Simplex Transmitter used in LX45T board and Simplex Reciever used in LX25T board.
3)GTP reference clock = 100MHz, lane speed = 1.25 Gbps
4)we are using ISE 14.5 version.
Please find the attached TX and EX project files.
05-26-2014 10:53 PM
05-21-2014 10:40 PM
05-26-2014 08:54 AM
sorry for late reply,these are the comments for your questions
Q1)Are you sure the connectivity between Tx and Rx is correct in case of Simplex link?
Ans)yes,Its correct.we tested using full duplex and same we reatained for testing simplex too.
Q2)What is the status of resetdone, rxbyteisaligned signals at the Simplex Rx?
Ans) resetdone is high.Regarding rxbyteisaligned ,most of times its zero and sometimes its going High.
Q3) Can you try asserting pma_init at the Rx, followed by RESET (not GT_RESET) input at Simplex Tx?
Ans)We are not finding any pma_init signal ,please let me know which module we can find it.
We have done same simplex testing in virtex-5 based boards.Below are the our observations.
Please suggest and let us know any parameters need to change for spartan-6 FPGA's.
05-26-2014 10:53 PM
05-27-2014 06:21 AM
We done according to your suggestion.,After this we saw lane up at receiver side ,but after sometime lane up is deasserting.These are the our observations
05-27-2014 08:04 PM
hi tarak,we are doing almost the same work now.
i am tring to use aurora duplex between two spartan 6 -45t FPGA based board, and encounter a problem that both lane up
and channel up failed.
then i test self-loop, connecting the TXP/TXN to RXP/RXN on one board, it works well.
is there any thing ignored in my design? and how could i check the problem?
aurora duplex framing mode/ streaming mode other parameter are set as default referred to board.
05-27-2014 09:52 PM
1)If your are using SFP module for communciation between two boards,Please check the what is the status of Tx-Disable and LOS signal of SFP module.Both signals should be zero.
2)I suggest you to check the two board connecvity using IBERT.This help us to know about the harware is fine or not.