UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
5,693 Views
Registered: ‎06-21-2010

Aurora with Virtex-6

Hi,

I'm trying to use Aurora with Virtex-6 LX240t. Example design is my test code generated by core generator (11.5 and 12.1). When I test it with loopback mode (near end PCS and PMA), both work fine. I turn off loopback and try to connect to outside FPGA. But I found that pins for GTX IO are not driven at all. How can I turn GTX IO on?

Thank you,

yoshi

 

0 Kudos
10 Replies
Xilinx Employee
Xilinx Employee
5,683 Views
Registered: ‎01-03-2008

Re: Aurora with Virtex-6

It sounds like the GTX locations in the Aurora core does not match your board.  I would suggest that you look in the PAD file for your design to confirm that they were placed correctly or by viewing the locations in FPGA Editor

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
5,669 Views
Registered: ‎06-21-2010

Re: Aurora with Virtex-6

Thank you for your suggestion. I re-checked Pinout report and connections seem OK...

 

BTW, iBERT test was successful with outer connections. Naively I think GTX is working and also the outer connections are OK. So I guess there is a switch to turn GTX on. Is there any secret for ES Virtex-6? Mine is ES...

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
5,663 Views
Registered: ‎01-03-2008

Re: Aurora with Virtex-6

If IBERT is working on the same GTX link then there isn't any reason why your Aurora design isn't also working.

 

There isn't a "switch" and there are a few Virtex-6 errata items for the GTX, but none of these should be an issue with your Aurora design.

 

The only suggestion that I could make at this point is to review how you are controlling the Aurora core.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
Adventurer
Adventurer
5,653 Views
Registered: ‎02-14-2009

Re: Aurora with Virtex-6

hello!

 

i have the same issue on ml605 sma's.

IBERT design work fine.

but aurora example_design (aurora v5.1) from Coregen (ISE 11.5 & 12.1) don't work at all.

behavioral simulation seems to be ok.

generated ucf file looks strange, there is no NET INIT_CLK constraint.

i used following ucf file:

and channel_up&lane_up not going to high(

 

on ml505 with virtex-5 lx50t all works fine.

 

what is wrong i do?

 

thanks

 

 


 # Reference clock contraint for GTX
NET GTXQ4_left_i PERIOD = 8.0 ns HIGH 50%;

# User Clock Contraint: the value is selected based on the line rate (3125Mbps) of the module
NET "user_clk_i" TNM_NET = USER_CLK;
TIMESPEC TS_user_clk_i = PERIOD "USER_CLK" 15.0 ns HIGH 50%;

NET GTXQ4_P LOC=H6;
NET GTXQ4_N LOC=H5;

# 50MHz board Clock Constraint
NET "reset_logic_i/init_clk_i" TNM_NET = INIT_CLK;
TIMESPEC TS_INIT_CLK = PERIOD "INIT_CLK" 15.0 ns HIGH 50%;

NET INIT_CLK LOC = U23; # U23 - 66Mhz clock source on ml605       # 200MHz - J9;



###### No cross clock domain analysis. Domains are not related ##############
TIMESPEC "TS_TIG1" = FROM "INIT_CLK" TO "USER_CLK" TIG;

################################ Resets Buttons #################################
NET RESET LOC=G26; #BUTTON #NET "GPIO_SW_C" LOC = "G26"; ## 2 on SW9 pushbutton (active-High)
NET RESET PULLUP;
NET GT_RESET_IN LOC=A18; #BUTTON #NET "GPIO_SW_S" LOC = "A18"; ## 2 on SW6 pushbutton (active-High)

################################ Errors Indicators ##############################
NET HARD_ERROR LOC=AE22; #LED #NET "GPIO_LED_2" LOC = "AE22"; ## 2 on LED DS9, 3 on J62
NET SOFT_ERROR LOC=AE23; #LED #NET "GPIO_LED_3" LOC = "AE23"; ## 2 on LED DS10, 4 on J62
NET FRAME_ERROR LOC=AB23; #LED #NET "GPIO_LED_4" LOC = "AB23"; ## 2 on LED DS15, 5 on J62

################################ Channel and Lane up Indicators #################
#This board supports a maximum of 12 lanes
NET CHANNEL_UP LOC=AC22; #LED #NET "GPIO_LED_0" LOC = "AC22"; ## 2 on LED DS12, 1 on J62
NET LANE_UP LOC=AC24; #LED #NET "GPIO_LED_1" LOC = "AC24"; ## 2 on LED DS11, 2 on J62
#######################################################################################
NET frame_check_i/* TIG;
#######################################################################################
INST aurora_module_i/gtx_wrapper_i/GTXE1_INST/gtxe1_i LOC=GTXE1_X0Y18;

 

0 Kudos
5,644 Views
Registered: ‎06-21-2010

Re: Aurora with Virtex-6

I guess there must be trivial mistakes somewhere in my codes but let me explain my situation.

 

 

Because I found that Virtex-6 FPGA CES silicon is not supported in ISE 12.1 GTX wizard (AR#34191), I used 11.5 first. I generated the core with Aurora 8B10B 5.1, 4lanes, lane width 2, Line rate 6.250 Gbps, GT refclk 156.25 Hhz, Duplex, Framing and no flow control. Virtex-6 is lx240t-2ff1759 and the quad I used was 112(X0Y0,X0Y1,X0Y2,X0Y3). I had several errors from the generated files in ISE11.5 so I modified followings.
1. aurora_8b10b_v5_1_clock_module.vhd : To avoid MMCM error
    constant MULT        : real    := 6.0; -- original is 2.0
    constant DIVIDE      : integer := 3;   -- original is 1
2. aurora_8b10b_v5_1_example_design.vhd : To work constraint
    signal user_clk_i         : std_logic;
    attribute S : string;                          -- added
    attribute S of user_clk_i : signal is "TRUE";  -- added
As I wrote, these changes worked in loopback modes. But I had no output from GTX. Same thing in ISE 12.1. This is my situation...

 

Because I found that Virtex-6 FPGA CES silicon is not supported in ISE 12.1 GTX wizard (AR#34191), I used 11.5 first. I generated the core with Aurora 8B10B 5.1, 4lanes, lane width 2, Line rate 6.250 Gbps, GT refclk 156.25 Hhz, Duplex, Framing and no flow control. Virtex-6 is lx240t-2ff1759 and the quad I used was 112(X0Y0,X0Y1,X0Y2,X0Y3). I had several errors from the generated files in ISE11.5 so I modified followings.


1. aurora_8b10b_v5_1_clock_module.vhd : To avoid MMCM error
    constant MULT        : real    := 6.0; -- original is 2.0

    constant DIVIDE      : integer := 3;   -- original is 1

 

2. aurora_8b10b_v5_1_example_design.vhd : To work constraint
    signal user_clk_i         : std_logic;

    attribute S : string;                          -- added

    attribute S of user_clk_i : signal is "TRUE";  -- added

 

As I wrote, these changes worked fine in loopback modes. But I had no output from GTX. Same thing in ISE 12.1. This is my situation...

0 Kudos
485 Views
Registered: ‎08-07-2017

Re: Aurora v5.2 ip instantiation problem with Virtex-6 ml605

hello sir, 

 I generated the core with Aurora 8B10B 5.2, 1 lanes, lane width 2, Line rate 3.125 Gbps, GT refclk 156.25 Hhz, Duplex, Framing and no flow control, in Xilinx ISE 13.2 version. after generation of HDL code of Aurora ip and instantiat wrapper in top design module. but when i run sysnthesis it gives error 

ERROR: Core Generator generated file aurora_1/src/aurora_1.vhd was not found.
ERROR: Core Generator generated file aurora_1/src/aurora_1.vhd was not found.
ERROR: Core Generator generated file aurora_1/src/aurora_1.vhd was not found.
ERROR: Unable to find top-level HDL source file for core: aurora_1.

thanks 

0 Kudos
Newbie jamielanger
Newbie
479 Views
Registered: ‎04-02-2019

Re: Aurora with Virtex-6

This was of great help "I would suggest that you look in the PAD file for your design to confirm that they were placed correctly or by viewing the locations in FPGA Editor"

0 Kudos
468 Views
Registered: ‎08-07-2017

Re: Aurora with Virtex-6

greate suggestion...... but when i am checking RTL schematic of design, this gives same error..................

0 Kudos
Moderator
Moderator
451 Views
Registered: ‎05-02-2017

Re: Aurora with Virtex-6

hi @toshas ,

 

for your query can please create new post .

 

Regards
Chandra sekhar
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if solution provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Adventurer
Adventurer
435 Views
Registered: ‎02-14-2009

Re: Aurora with Virtex-6

Hi, @csattar !

I think you are talking to someone else.
My problem was solved many years ago.

Best regards.

0 Kudos