08-18-2020 06:09 AM
I'm working on an Ethernet design, on Zynq UltraScale+ MPSoC device. My design consists of AXI Ethernet Subsystem which is connected via GMII interface to "Gmii to Rgmii v4.0" IP which is then connected to PHY by RGMII interface.
I know that Axi Ethernet Subsystem could be directly connected to PHY by RGMII, but the GMII interface is design requirement - in the future, we will add IP for traffic monitoring which can only be connected to the GMII interface.
Currently, I'm in the process of testing design functionality and I run into problems with Ethernet RX path. By performing iperf test on my device I discovered ~6% packet loss on the RX path. To find the source of the issue I performed some tests/analyses and I came to some assumptions.
I tried the following:
According to the performed analyses and tests, I suspect that issue could be on the GMII interface.
08-18-2020 01:44 PM
Hi @nikorenic ,
GMII to RGMII shim IP is supposed to be used with PS GEM only to provide an RGMII interface to PHY. It's not designed to be interfacing any other IPs such as AXI Ethernet subsystem IP. As you are also aware that this IP supports RGMII already.
This is not a supported HW design and has never been tested.
We have not seen any GMII issues on AXI Ethernet subsystem IP on its own.