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Visitor
Visitor
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Registered: ‎10-12-2018

Axi Ethernet Subsystem + Gmii to Rgmii - RX path issue

Hi all,

I'm working on an Ethernet design, on Zynq UltraScale+ MPSoC device. My design consists of AXI Ethernet Subsystem which is connected via GMII interface to "Gmii to Rgmii v4.0" IP which is then connected to PHY by RGMII interface.
I know that Axi Ethernet Subsystem could be directly connected to PHY by RGMII, but the GMII interface is design requirement - in the future, we will add IP for traffic monitoring which can only be connected to the GMII interface.

design_axi_eth_gmii2rgmii.png

Currently, I'm in the process of testing design functionality and I run into problems with Ethernet RX path. By performing iperf test on my device I discovered ~6% packet loss on the RX path. To find the source of the issue I performed some tests/analyses and I came to some assumptions. 
I tried the following:

  1. Tested design where Axi Ethernet Subsystem is directly connected to PHY (no "Gmii To Rgmii" IP) - with this design we did not have RX packet loss 
  2. Tested design where PS GEM is connected to "Gmii To Rgmii" IP - with this design we also did not have RX packet loss
  3. Checked RGMI TX/RX 2ns clock skew - OK - TX/RX 2ns skew is enabled only in PHY, it is disabled on other components
  4. Tunning RGMII RX Constraints - I changed set_input_delays to the values which are defined by our PHY but this did not resolve the RX path issue

According to the performed analyses and tests, I suspect that issue could be on the GMII interface.

My questions:

  1. In "Gmii to Rgmii" documentation it is written that IP is designed to work with Zynq GEM. Is there any reason why this IP should not work in conjunction with other IPs (eg. Axi Ethernet Subsystem)?
  2. Are there any special constraints needed for the GMII interface? (in the documentation are given examples only for RGMII)

Thank You!

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @nikorenic ,

GMII to RGMII shim IP is supposed to be used with PS GEM only to provide an RGMII interface to PHY. It's not designed to be interfacing any other IPs such as AXI Ethernet subsystem IP. As you are also aware that this IP supports RGMII already. 

This is not a supported HW design and has never been tested.

We have not seen any GMII issues on AXI Ethernet subsystem IP on its own.

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