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fincs
Adventurer
Adventurer
1,467 Views
Registered: ‎03-21-2016

Axi Ethernet not receive data

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Hi all

I'm have problem wth AxiEthernet Core.

Core config
- Ethernet Speed 1 Gbps
- Physical Interface 1000 Base X
- MDIO Phy Address 1
- Shared logic : Include Shared Logic in IP Example Design (IBUFDS_GTE2 move in top level).


I'm use the next scheme. PCI Express core with 250 MHz and PCI Express Reset connent to my MMCME2_ADV. MMCME2_ADV perform reference clock 200 MHz, Axi Stream clock 125 MHz and Axi Lite clock 125 MHz. Axi lite reset and axi stream reset duration 296 ns.

Configuring phy level

1) Addr 0x500 write Data 0x00000068
2) Read addr 0x504, wait bit 7
3) Read addr 0x500
4) Addr 0x508 write Data 0x00000000
5) Addr 0x504 write Data 0x01004800
6) Read addr 0x504, wait bit 7
7) Addr 0x504 write data 0x01008800
8) Read 0x50C, wait bit 16.
9) Configure phy complete


Configure mac level
1) wait Configure phy complete
2) Addr 0x404 Write Data 0x90000000
3) Addr 0x408 Write Data 0x90000000
4) Addr 0x70C write Data 0x00000000
5) Addr 0x40C write data 0x60000000
6) Configure mac complete

Auto-Negotiation disable. Other network device also Auto-Negotiation disable. If send packet to network, out gtx RxCharISK and RxData have correct data (i'm view only preamble), GMII_RXD and GMMI_RX_DV not have data, always zero.

If remove core AxiEthernet and add core Ethernet PCS/PMA or SGMII, then GMII_RXD and GMMI_RX_DV have data. Configure vector of PCS/PMA have all zero.

 

Kintex 7. Vidado 2016. 4

What am I doing wrong?

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fincs
Adventurer
Adventurer
1,542 Views
Registered: ‎03-21-2016

I'm solved a problem. 

After adjusting the core, the gtrefclk signal changed. As a result, a SRESET was generated and the kernel needed to be reconfigured.

View solution in original post

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fincs
Adventurer
Adventurer
1,400 Views
Registered: ‎03-21-2016

Update

If I wait 8 seconds after resetting and configure phy and ethernet core, everything works.

I added the debugger and saw that if I set up right after the reset, the configuration is successful. However, later there is still a SRESET.

The signal SRESET becomes active due to the signal locked in  axi_ethernet_0_support_clocks.v/mmcm_adv_inst becomes zero.

TXRESETDONE.PNG
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dpaul24
Scholar
Scholar
1,387 Views
Registered: ‎08-07-2014

@fincs,

 

GMII_RXD and GMMI_RX_DV not have data, always zero. -- so here is the problem!

 

Now you have to investigate why there is no proper rx data. Plz debug your PHY!

------------FPGA enthusiast------------
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fincs
Adventurer
Adventurer
1,543 Views
Registered: ‎03-21-2016

I'm solved a problem. 

After adjusting the core, the gtrefclk signal changed. As a result, a SRESET was generated and the kernel needed to be reconfigured.

View solution in original post

0 Kudos