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Registered: ‎11-29-2019

Axi_ethernet 3.1 AVB on a virtex 6 ml605 board

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Hello everyone,

I am trying for some time now to use the AVB functionality of the axi_ethernet 3.1 core in the EDK version 14.4. I found the AVB examples and I added the ethernet core to my XPS project. I then checked the "Audio video briding" checkbox in the IP configuration. The export does not show any errors. When using the SDK the xavb.h and xavb.c files dont show up, which are needed for the examples.

I took a look at my design and it seems like the AXI_STR_AVB... signals are not connected at all. How and where do I connect those? Is there any tutorial or the like to this?

As to what I am trying to do: I want to connect the ethernet core (with AVB) to my microblaze to create PTP traffic and syncronize other machines clocks with it (the ML605 would be my static grand master).

A note: Using the manual (https://www.xilinx.com/support/documentation/ip_documentation/axi_ethernet/v3_01_a/ds759_axi_ethernet.pdf) I got confused, since AXI_STR_AVBTX_ACLK was marked as input but the core displays it as an output. Is that an error in the core or did I do something wrong?

Thank you for your time already.

Sincerly,

Christian

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230 Views
Registered: ‎11-29-2019

Re: Axi_ethernet 3.1 AVB on a virtex 6 ml605 board

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If you want to reconstruct what I got so far, here are the steps:

Tested with EDK 13.4 and 14.4

In XPS:
-> Create base builder project
-> Change the eth_lite to the Ethernet
-> Generate the project
-> Goto "System assembly view"
-> Right click ETHERNET and select "Configure IP..."
-> Enable AVB (if not already)
-> Do not enable any VLAN capability since none of them are compatible!
-> Enable "Statistics Counters" (optional)
-> Go to "System assembly -> Ports"
-> Connect RTC_CLK to the clock_generator Port 0 (100 MHz), it needs at least 25 MHz (Xilinx recommends 125 MHz, which would be Port 1)
-> Set "Type of TEMAC" from "v6 Hard TEMAC" to "Soft TEMAC 10/100/1000 Mbps lic req"
-> AVB is not compatible with the Hard TEMAC since EDK 14.1!
-> If you use EDK 13.4 or lower you can use the Hard TEMAC instead (no license required)
-> I had timing issues regarding version 13.4 that I could not resolve!
-> For testing purposes you can disable "Treat timing closure failure as an error"
-> The option is under Project -> Project Options -> Design Flow -> Design Flow Options
-> Connect AV_INTERRUPT_10MS, AV_INTERRUP_PTP_TX and AV_INTERRUP_PTP_RX to the interrupt controller
-> Generate Bitstream and export to SDK

In SDK:
-> Create a new project (if not existent already)
-> Create a new folder and call it "avb" (optional)
-> Import all example files from "...\Xilinx\ISE\13.4\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\axiethernet_vx_xx_a\examples\avb"
(where x is your version number) into your project folder
-> If not existent, create a new BSP (Right click -> New -> Other -> Xilinx -> Board support package -> Next until finished)
and make sure to reference it with your project
-> Right click on the project folder and select "Change referenced BSP" and select your BSP
-> If you got issues creating the Board Support Package:
->Right click in the project explorer -> New -> Project...
=> Xilinx -> Board Support Package -> Next -> Finish

-> Program your FPGA (in the toolbar: Xilinx Tools -> Program FPGA -> Press Program
-> Connect to the FPGA (via Putty or Teraterm or the like)
-> You can check the COM port in the windows hardware manager (mine was COM6)
-> Run your program
-> If not setup already: Run -> Run configuration -> Xilinx C/C++ Elf -> Run
-> The console (if connected correctly) should show you the output of the example
-> It should end with "Example passed" and "--- Exiting main() ---"

View solution in original post

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Registered: ‎11-29-2019

Re: Axi_ethernet 3.1 AVB on a virtex 6 ml605 board

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Ok, I got the example to work. I changed the ethernet IP to use AVB and then connected the three interrupts AV_INTERRUPT_10MS, AV_INTERRUP_PTP_TX and AV_INTERRUP_PTP_RX to my interrupt controller. After that I created the bitstream and exported it to the SDK. Then I imported all the example files (located at ...\Xilinx\ISE\13.4\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\axiethernet_vx_xx_a\examples\avb") and programmed my FPGA. After that I could start the example which finished with "Example passed". I still dont know if PTP works in general, but it seems like I am making progress

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231 Views
Registered: ‎11-29-2019

Re: Axi_ethernet 3.1 AVB on a virtex 6 ml605 board

Jump to solution

If you want to reconstruct what I got so far, here are the steps:

Tested with EDK 13.4 and 14.4

In XPS:
-> Create base builder project
-> Change the eth_lite to the Ethernet
-> Generate the project
-> Goto "System assembly view"
-> Right click ETHERNET and select "Configure IP..."
-> Enable AVB (if not already)
-> Do not enable any VLAN capability since none of them are compatible!
-> Enable "Statistics Counters" (optional)
-> Go to "System assembly -> Ports"
-> Connect RTC_CLK to the clock_generator Port 0 (100 MHz), it needs at least 25 MHz (Xilinx recommends 125 MHz, which would be Port 1)
-> Set "Type of TEMAC" from "v6 Hard TEMAC" to "Soft TEMAC 10/100/1000 Mbps lic req"
-> AVB is not compatible with the Hard TEMAC since EDK 14.1!
-> If you use EDK 13.4 or lower you can use the Hard TEMAC instead (no license required)
-> I had timing issues regarding version 13.4 that I could not resolve!
-> For testing purposes you can disable "Treat timing closure failure as an error"
-> The option is under Project -> Project Options -> Design Flow -> Design Flow Options
-> Connect AV_INTERRUPT_10MS, AV_INTERRUP_PTP_TX and AV_INTERRUP_PTP_RX to the interrupt controller
-> Generate Bitstream and export to SDK

In SDK:
-> Create a new project (if not existent already)
-> Create a new folder and call it "avb" (optional)
-> Import all example files from "...\Xilinx\ISE\13.4\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\axiethernet_vx_xx_a\examples\avb"
(where x is your version number) into your project folder
-> If not existent, create a new BSP (Right click -> New -> Other -> Xilinx -> Board support package -> Next until finished)
and make sure to reference it with your project
-> Right click on the project folder and select "Change referenced BSP" and select your BSP
-> If you got issues creating the Board Support Package:
->Right click in the project explorer -> New -> Project...
=> Xilinx -> Board Support Package -> Next -> Finish

-> Program your FPGA (in the toolbar: Xilinx Tools -> Program FPGA -> Press Program
-> Connect to the FPGA (via Putty or Teraterm or the like)
-> You can check the COM port in the windows hardware manager (mine was COM6)
-> Run your program
-> If not setup already: Run -> Run configuration -> Xilinx C/C++ Elf -> Run
-> The console (if connected correctly) should show you the output of the example
-> It should end with "Example passed" and "--- Exiting main() ---"

View solution in original post

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Registered: ‎08-25-2009

Re: Axi_ethernet 3.1 AVB on a virtex 6 ml605 board

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Hi @studentchristian ,

Can you please mark your own thread as "Accepted solution" so it will benefit other forum users too? 

 

"Don't forget to reply, kudo and accept as solution."
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