09-27-2018 07:17 AM
i want to instantiate the "1G/2.5G Ethernet PCS/PMA or SGMII" IP on the Ultrascale xcku040. I'm using Vivado 2017.4
During the Implementation i get the following Error:
[Place 30-689] Failed to place BITSLICE_CONTROL cell gig_eth_pcs_inst_asyn/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl on site BITSLICE_CONTROL_X1Y25 because Instance gig_eth_pcs_inst_asyn/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl can not be placed in CONTROL of site BITSLICE_CONTROL_X1Y25 because the bel is occupied by gig_eth_pcs_inst_asyn/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_1.Nibble_I_BitsliceCntrl(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.
It seems that vivado wants to take the same BitsliceCntrl for TX and RX. But this is not possible.
How can i solve this Problem? I'm not very familar with the Bitslice concept.
It tried to move the RX BitsliceCntrl to another Place (for example BITSLICE_CONTROL_X1Y24) but it doesnt work.
Here is a screenshot of my IP GUI settings:
Maybe it has to do something with the IO Placement Options?
Here are my constraints regarding the LVDS Pins:
set_property PACKAGE_PIN J9 [get_ports sgmii_0_rxp] set_property PACKAGE_PIN H9 [get_ports sgmii_0_rxn] set_property IOSTANDARD LVDS [get_ports sgmii_0_rxn] set_property IOSTANDARD LVDS [get_ports sgmii_0_txp] set_property PACKAGE_PIN F10 [get_ports sgmii_0_txp] set_property PACKAGE_PIN F9 [get_ports sgmii_0_txn] set_property IOSTANDARD LVDS [get_ports sgmii_0_txn]
I appreciate any kind help. Thank you guys
09-27-2018 09:06 AM
10-02-2018 03:50 AM
thx for the link. it is very helpful.
I think the Problem that i have is that the RX and TX are in the same Lower Nibble of the Byte Group.
And this isn't allowed, am i right?
Because if i change the Pins for RX, it seems to work...