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Visitor
Visitor
8,816 Views
Registered: ‎05-24-2014

Block Memory Generator 8.2 depth constraints

I am trying to generate a 12-bit wide by 307200 deep block memory on an Artix 7 (XC7A100T).  The memory needs to be a single-port ROM.  In ISE 14.7 with Block Memory Generator 7.3, this is possible and works fine, but in Vivado 2014.1 with Block Memory Generator 8.2 this is not possible.  The datasheet for BMG 8.2 shows (in table 1-1) that for data widths less than 128 bits, the maximum depth is 128k, less than half of what I need.  Why does this limitation exist in BMG 8.2, and is there any way to get around it? I could use a larger width and acheive the same total storage size, but that complicates the design.

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Guide
Guide
8,792 Views
Registered: ‎01-23-2009

A RAM this size will require a HUGE number of block RAMs. Assume they end up getting built by 32Kx1 RAMs (which is probably the most efficient), this will require 120 block RAMs. The Artix-7 100T has only 135 RAMs, so this is nearly all the RAMs that exist within the device.

 

Except at REALLY slow speeds, its unlikely that you would be able to fan-out the address to all 120 RAMs within the same clock cycle and gather the data to MUX together - particularly since the RAMs fairly literally span the entire die (so your routing will go nearly corner to corner). Its probably not possible to make this work in one clock cycle, which is why the memory generator doesn't just blindy build it.

 

However, if you can tolerate several clocks of latency, you can probably do this manually (without the block memory generator). You will need to pipeline your address and write data to the RAMs, and probably manually replicate them to reach the 120 RAMs. You will need to do something similar with the read data and the multiplexing. At a "reasonable" speed (say 100MHz), this will likely require something like 4 clock cycles for the complete read operation.

 

Avrum

 

 

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Visitor
Visitor
8,773 Views
Registered: ‎05-24-2014

I understand that this is by no means an efficient design, but it only needs to run at 25 MHz - the application is to store a video buffer.  Like I said, I have used ISE's Block Memory Generator 7.3 to successfully implement the design, so I was just curious as to the reason there was a soft limit in BMG 8.2.

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Xilinx Employee
Xilinx Employee
8,755 Views
Registered: ‎08-01-2008

Current version of block memory generator has depth limitation .

I think you can generate the smaller memory and cascade to create higher depth
Thanks and Regards
Balkrishan
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