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Scholar samcossais
Scholar
10,648 Views
Registered: ‎12-07-2009

Bug(s) with SRIO Gen2 v3.1

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Hi

I am evaluating SRIO Gen2 v3.1 (Vivado 2014.1) right now and I found a bug with TXDIFFCTRL which is 4b on some files while it is 3b on others. According to the GTX user guide, the port on GTX is 4b.

 

Its value is set to 4'b1000 in synth/<srio_gen2_core_name>block.v, while some wrappers below use only 3b, therefore I suppose the value finally used by the GTX will be truncated and be 4'bz000, with bit 4 being undriven. I could check it in simulation and it is the case.

 

I made the SRIO core using Vivado 2014.1 IP catalog, with the "additional transceiver control and status ports" unchecked.

 

I believe this is a serious problem as it controls the differential voltage on the TX driver, which is a very important parameter.

 

How can I correct this problem ?

Should I just correct the verilog files in my IP folder (<ip_name>/synth) ?

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Scholar kotir
Scholar
16,824 Views
Registered: ‎02-03-2010

Re: Bug(s) with SRIO Gen2 v3.1

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Hi ,

 

This is a known issue in the core for v3.1.

 

This issue can be resolved by modifying the width on assignment as 3:0 (4 bit) in place of 2:0 (3 bit) for all the places it appers in the srio gt wrapper file.

Can you try it ?

 

Regards,

KR

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Scholar kotir
Scholar
16,825 Views
Registered: ‎02-03-2010

Re: Bug(s) with SRIO Gen2 v3.1

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Hi ,

 

This is a known issue in the core for v3.1.

 

This issue can be resolved by modifying the width on assignment as 3:0 (4 bit) in place of 2:0 (3 bit) for all the places it appers in the srio gt wrapper file.

Can you try it ?

 

Regards,

KR

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Scholar samcossais
Scholar
10,617 Views
Registered: ‎12-07-2009

Re: Bug(s) with SRIO Gen2 v3.1

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Thank you very much for your reply. I did the modification. Should I rerun the "out of context module run" for it ? I previously had to remake my Vivado project  and since then my srio core is no longer listed in the "out of context module runs" list.

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Scholar kotir
Scholar
10,611 Views
Registered: ‎02-03-2010

Re: Bug(s) with SRIO Gen2 v3.1

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Hi ,

 

I guess as you are modifying the RTL, you need to redo the synthesis.

 

Not sure if that list does not show the out of dated runs as the above modification would result in synthesis products our of date.

 

Regards,

KR

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Scholar samcossais
Scholar
10,606 Views
Registered: ‎12-07-2009

Re: Bug(s) with SRIO Gen2 v3.1

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I guessed so too. I don't know why neither but this did not show inside the runs list. Do you have any way to run a particular ooc synthesis by yourself, without it being inside the list beforehand ?

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Scholar kotir
Scholar
10,602 Views
Registered: ‎02-03-2010

Re: Bug(s) with SRIO Gen2 v3.1

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Hi ,

 

Can you put the snapshot what you are looking in the GUI of the tool ?

 

I believe the design runs section in the tool gui lists all the design runs including the ooc's.

 

Regards,

KR

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Scholar samcossais
Scholar
10,596 Views
Registered: ‎12-07-2009

Re: Bug(s) with SRIO Gen2 v3.1

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Can you put the snapshot what you are looking in the GUI of the tool ?



Here it is.

 

Edit: As you can see the implementation is out of date. This is due to the fact that I have some IPs that are common to 2 FPGAs, one being a xc7k 160t-fbg676-2 and another one being a xc7k 160t-fbg484-1

For those common IPs, I kept the version in the xc7k 160t-fbg484-1 which was compiled in the project for this one, hence these out of date warnings. Anyway this does not include the srio core which is present only in the xc7k 160t-fbg676-2 FPGA.

vivado_runs_no_srio.png
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Scholar samcossais
Scholar
10,588 Views
Registered: ‎12-07-2009

Re: Bug(s) with SRIO Gen2 v3.1

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I believe the design runs section in the tool gui lists all the design runs including the ooc's.

It looks like it includes the ooc runs but not all.

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Scholar kotir
Scholar
10,584 Views
Registered: ‎02-03-2010

Re: Bug(s) with SRIO Gen2 v3.1

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Hi

 

I guess you did not enabled the ooc option while generating the core. are you sure of it ?

 

 

regards,

KR

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Scholar samcossais
Scholar
10,574 Views
Registered: ‎12-07-2009

Re: Bug(s) with SRIO Gen2 v3.1

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I am quite sure I did (I always left this setting to default), the thing is I remade my project in between. It appears to be the same for some other IPs as well, some are not listed in the design runs list.

 

But, I was able to check that the modification on the core was well taken into account anyway :

srio_gtx_setting.PNG
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