cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor
Visitor
260 Views
Registered: ‎02-26-2019

Building ethernet functionality on Styx board using EMIO and RGMII PHY

Hello,

 

I have two hardwares for implementing ethernet on zynq via EMIO, Numato Lab's Zynq board - Styx and Numato Lab's Gb Ethernet Module - RTL8211E.

https://numato.com/product/styx-zynq-7020-fpga-module

https://numato.com/product/rtl8211e-gigabit-ethernet-expansion-module

I also have Numato Lab's Galatea Gb Ethernet Module - RTL8211E on Hirose connector:

https://numato.com/product/galatea-rtl8211e-gigabit-ethernet-expansion-module.

The hardware choice was not for me to decide and now I need to implement ethernet on this zynq board using EMIO as MIO are not available except UART on the board. I also have zc702 for testing and validation of readymade interfaces but the assigned task seems completely different than implementing ethernet on zc702. I have developed and burned bit file and a block diagram is shown in attached snap.

ethernet for styx using emio.PNG

There were some errors regarding rxd_clk pin in constraint file so I had to provide an additional constraint for clock generation as :

create_clock -period 8.000 -name RGMII_0_rxc -waveform {0.000 4.000} [get_ports RGMII_0_rxc]

-------xdc file-------

#set_property -dict { PACKAGE_PIN "A16"    IOSTANDARD LVCMOS33   SLEW FAST} [get_ports { RGMII_rxc }]     ;
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports UART_0_rxd]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports UART_0_txd]
create_clock -period 8.000 -name RGMII_0_rxc -waveform {0.000 4.000} [get_ports RGMII_0_rxc]
##################################################################################################################################################
#                                                           Intr Rst MDIO IO                                                                     #
##################################################################################################################################################

set_property PACKAGE_PIN H19 [get_ports ENET1_EXT_INTIN_0]
set_property IOSTANDARD LVCMOS33 [get_ports ENET1_EXT_INTIN_0]
set_property PACKAGE_PIN K18 [get_ports FCLK_RESET0_N_0]
set_property IOSTANDARD LVCMOS33 [get_ports FCLK_RESET0_N_0]
set_property PACKAGE_PIN M17 [get_ports mdio_phy_io_0]
set_property IOSTANDARD LVCMOS33 [get_ports mdio_phy_io_0]
set_property PACKAGE_PIN L17 [get_ports mdio_phy_mdc_0]
set_property IOSTANDARD LVCMOS33 [get_ports mdio_phy_mdc_0]
##################################################################################################################################################
#                                                               RGMII  IO                                                                        #
##################################################################################################################################################
set_property PACKAGE_PIN H20 [get_ports {RGMII_0_rd[3]}]
set_property PACKAGE_PIN H22 [get_ports {RGMII_0_rd[2]}]
set_property PACKAGE_PIN F17 [get_ports {RGMII_0_rd[0]}]
set_property PACKAGE_PIN G22 [get_ports {RGMII_0_rd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_rd[0]}]
set_property PACKAGE_PIN C15 [get_ports {RGMII_0_td[0]}]
set_property PACKAGE_PIN B15 [get_ports {RGMII_0_td[1]}]
set_property PACKAGE_PIN D16 [get_ports {RGMII_0_td[2]}]
set_property PACKAGE_PIN D17 [get_ports {RGMII_0_td[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGMII_0_td[0]}]
set_property PACKAGE_PIN G17 [get_ports RGMII_0_rx_ctl]
set_property PACKAGE_PIN D18 [get_ports RGMII_0_rxc]
set_property PACKAGE_PIN A17 [get_ports RGMII_0_txc]
set_property PACKAGE_PIN D21 [get_ports RGMII_0_tx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rx_ctl]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_rxc]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_txc]
set_property IOSTANDARD LVCMOS33 [get_ports RGMII_0_tx_ctl]

#set_property PACKAGE_PIN A16 [get_ports rgmii_rxc]
#set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]
#set_property PACKAGE_PIN D18 [get_ports rgmii_rxc]
#set_property IOSTANDARD LVCMOS33 [get_ports rgmii_rxc]

------------------------

Please tell if it is correct or what else can be done.

AFAIK there may be another approach where MAC can be implemeted in PL section abd that would need either xilinx IP core for that or expertize to generate one. Both are not available :-)

Another approach may be to use UART and then using an ethernet converter. It would limit max speed to 40Mbps.

Another approach may be to use ethernet module (ENC28J60) with MAC and PHY and that is available with SPI header. Here also speed limit is 25Mbps but it sems feasible.

 

It would be a great help if block diagram can be shared for the primary approach or corrections can be suggessted in my BD and constraint file.

For last approach, I would like to know if EMIOs for SPI can be directly taken out on GPIOs of PL and the using ENC28J60.

thanks in advance.

 

ethernet for styx using emio.PNG
0 Kudos
 
0 Kudos
4 Replies
Highlighted
Moderator
Moderator
233 Views
Registered: ‎08-25-2009

Re: Building ethernet functionality on Styx board using EMIO and RGMII PHY

Hi @rahulrana ,

What is the exact issue you are facing? The constraints seem OK.

If you are looking for a PL solution, Xilinx provides 1G/2.5G AXI Ethernet subsystem which you can use. Then you do not need to use GMII2RGMII IP.

 

"Don't forget to reply, kudo and accept as solution."
0 Kudos
Highlighted
Visitor
Visitor
208 Views
Registered: ‎02-26-2019

Re: Building ethernet functionality on Styx board using EMIO and RGMII PHY

Thanks @nanz ,

for your quick reply.

To be precise: I'm not able to get ethernet connectivity and echo back after deploying lwIP application. On serial debugger it says that autonegotiation failed.

I'm using Eth1 of Zynq PS and EMIO and then GMII to RGMII IP core for interfacing external PHY. This is indicated in block diagram.

If I have a choice I wouldn't want to go for AXI (as told by you) when I can work with EMIO. (I'm quite new to it so I'm not confident).

For your reference I want exactly what @teroki asked in :

https://forums.xilinx.com/t5/Processor-System-Design/Zynq-2nd-ethernet-to-EMIO-RGMII/m-p/794062/highlight/false#M24319

I didn't get the solution though.

0 Kudos
Highlighted
Moderator
Moderator
194 Views
Registered: ‎08-25-2009

Re: Building ethernet functionality on Styx board using EMIO and RGMII PHY

Hi @rahulrana ,

LWIP does not support all PHYs. Please check this AR on how to initialize the PHY.

https://www.xilinx.com/support/answers/63495.html

 

"Don't forget to reply, kudo and accept as solution."
0 Kudos
Highlighted
Visitor
Visitor
161 Views
Registered: ‎02-26-2019

Re: Building ethernet functionality on Styx board using EMIO and RGMII PHY

Ho,

That problem was an older one and the thread referred is also quite old. The NUmato board I'm using uses RealTek PHY RT8211E. That note was for lwIPv1.21 but now I'm using lwIP2.02_v1.1. where it itself has taken care of realTek PHY as attached.

 

lwIP snap - for realTekPHY.png
0 Kudos