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dck140130
Contributor
Contributor
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Registered: ‎02-06-2018

Bus Interface property CLK_Domain not matching between two trimode macs

I am using vivado 2018.1 and working with an AC701 Artix-7 board. I'm also an uber noob.

The error I am getting when I try to validate the design or generate a wrapper is:

 

 

 

ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /tri_mode_ethernet_mac_1/s_axis_tx(/clk_wiz_0_clk_out1) and /tri_mode_ethernet_mac_0/m_axis_rx(/tri_mode_ethernet_mac_0/rx_mac_aclk)

 

 

 

The design is currently built in IP Integrator and an image of the design is attached.

I pulled much of the design from PG047 (pages 91,155 and 159), and PG051 (pages 75 and 161 and 176). Any guidance would be greatly appreciated.

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projectDesign.jpg
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5 Replies
nanz
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Registered: ‎08-25-2009

Hi @dck140130 ,

Are you trying to use shared logic between two MACs? Your screenshot is not clear and I cannot seem to expand it to take a look. Could you please attach it again? 

Just an FYI, to avoid the manual connection between TEMAC and PCS/PMA core, you can use AXI Ethernet Subsystem IP in "non-processor" mode. 


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dck140130
Contributor
Contributor
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Registered: ‎02-06-2018

Hi @nanz,

Thank you so much for your consideration and reply. I have uploaded a more clear image with updated design.

I am trying to get the axi side of two trimode macs to talk to eachother.

I have not yet had a chance to  play with implementation of the AXI Ethernet Subsystem IP, but have seen other threads using it in their designs. It looks like a more complicated implementation to me. Then again, I don't know what my design will look like when it is complete. If you have the time, could you share the trade offs between my design and using AXI Ethernet Subsystem IP?

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nanz
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Registered: ‎08-25-2009

Hi @dck140130 ,

The CLOCK_DOMAIN can be checked in the block interface properties:

nanz_0-1612175373335.png

Can you please check based on the error message for the two interfaces in your design and see if it's possible to fix? 

To use AXI Ethernet Subsystem, you will no need to manual connect TEMAC with PCS/PMA. You can generate the IPs with the interfaces you need directly. Btw, I am not sure what you are trying to do with two stream interfaces connected together. Most customers will use FIFO or DMA in a processor system. In non-processor system, you may need additional FIFO for adding back pressure and avoid frames drop. 


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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dck140130
Contributor
Contributor
311 Views
Registered: ‎02-06-2018

Hi @nanz ,

Thank you for your continued guidance. I have confirmed that the clk domain properties differ between the s_axis_tx and m_axis_rx of Mac 0 and Mac 1. Do you happen to know how I close timing between the two domains?

The goal of this project is to use the AC701 for optical-ethernet media conversion. The left most ethernet mac will be used for the ethernet phy, while the right ethernet mac talks to the 1000 basex pcs/pma with sfp transceiver that communicates with the sfp connector housing the optical module. We will use a host pc running packet generator and sniffer as well as optical loopback on the optical module to demonstrate end to end transmission capabilities.

dck140130_0-1612311347564.pngdck140130_1-1612311397309.png

 

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nanz
Moderator
Moderator
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Registered: ‎08-25-2009

Hi @dck140130 ,

m_axis_rx interface is in rx_mac_aclk domain, s_axis_tx is on tx_mac_aclk domain. It's not allowed to connect different clock domains signal directly, what is why the error.

Normally the AXIS interface will attach to a FIFO or DMA, this is to add back pressure to avoid packet loss. You can try to add it in your design too if this will suit your application?


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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