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Visitor dinker
Visitor
761 Views
Registered: ‎02-15-2018

CPRI AxC MAPPING for eutra 20Mhz 2x2 Mimo

Hi Everyone,

 

Iam Using Cpri 8.6 example design as a start point. My question is how is sampling rate (30.72Msps here) is taken care while mapping to Xilinx provided E-utra Module in example design. 

 

Line rate is 4.9152Gbps. 20Mhz 2x2 mimo

15 bit I & Q

 

As per my understanding for there will be 2 Antenna Carriers

Oversampling ratio n =8 (30.72e6/3.84e6) (we can put 8 samples in one basic frame)

Core clock for 32bit data path is 122.88mhz

(please correct if i am wrong)

 

So is it right to set generic parameters in "iq_module_eutra . vhd" like

-- Channel #1 widths and number of samples.
C_TX_WIDTH_1 : natural := 15;
C_TX_S_1 : natural := 8;
C_RX_WIDTH_1 : natural := 15;
C_RX_S_1 : natural := 8;

-- Channel #2 widths and number of samples.
C_TX_WIDTH_2 : natural := 15;
C_TX_S_2 : natural := 8;
C_RX_WIDTH_2 : natural := 15;
C_RX_S_2 : natural := 8;

 

Because if i set Parameter like above then 8 samples would be mapped successively to the 8 channels of the utraFDD module but as they coming @ 30.72 msps they can not be mapped successively .

 

So please Kindly suggest how could i map the IQ stream at 30.72msps. 

 

Thanks in advance

 

BR

Dinker

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1 Reply
Xilinx Employee
Xilinx Employee
713 Views
Registered: ‎08-02-2007

Re: CPRI AxC MAPPING for eutra 20Mhz 2x2 Mimo

Hi @dinker the core clock depends on the line rate. For 4.9152Gbps line rate, you can refer to the section Supporting Line Rates up to 6,144.0 Mb/s and Figure 4-2 in pg056. For 32bit data path, 4.9152Gbps, 122.88mHz is correct.

 

For IQ module mapping based on your settings, please refer to Figure 3-25, 3-26 and 3-27.

 

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