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1,444 Views
Registered: ‎08-10-2016

Can I use MMCM to provide for single-ended GTREFCLK1 Aurora?

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Hi all,

 

I am relatively new to FPGA designing and am trying to design a high speed serial link using Aurora 8b/10b core on an Artix-7 FPGA (xc7a200tfbg676-2) on a custom board. My design consists of 2 Aurora 8b/10b cores, one configured with "Shared Logic In Core" (let's call it core-A) and the other with "Share Logic in Example Design" (let's call it core-B). Both the cores are configured for 4-byte streaming interface, 0.5Gbps line rate (trying slowest possible), 125MHz refclk and 100MHz init_clk. The cores are mapped to bottom row and single lanes (GT Selection). Core-A is mapped to GT0 X0Y0 and core-B to GT0 X0Y1. Both cores are configured to Near-end PMA loopback (loopback port = "010"). The Power-on, reset-sequence is as per the Aurora 8b/10b PG046.

 

The core-A is configured to have a single-ended GTREFCLK1. I am providing clock to this port through the output of a clock-wizard. Core-B gets its clocks from core-A, but GTREFCLK1 of core-B is connected to the same clock-wizard output. I have done so due to the fact that when Single-Ended REFCLK option is selected (core-A), the gt_refclk_out port is not present on core-A. I am using a clock-wizard because in the hardware, the differential MGTREFCLK pins are left unconnected and I don't want to add another external clock source. The near-end PMA loopback (also near-end PCS loopback) works only for core-A. Core-B never asserts channel-up and there are too many hard errors in core-B loopback (even though it is internal). No other loopbacks work. Hardware loopback doe not work either.

 

I read this answer record (https://www.xilinx.com/support/answers/53500.html) and understood that jitter levels are too much on internal FPGA clock nets. And I know MGTREFCLK_p/n pins are dedicated clock pins.

 

My questions are:

1. Is there a way to use an MMCM output as GTREFCLK in Aurora 8b/10b core?

2. Is it absolutely necessary to use MGTREFCLK_p/n pair for GTREFCLK?

3. How do MGTREFCLK pair pins differ from the internal FPGA clock nets in terms of jitter?

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Xilinx Employee
Xilinx Employee
2,050 Views
Registered: ‎08-01-2008

Re: Can I use MMCM to provide for single-ended GTREFCLK1 Aurora?

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No Xilinx recommends using a clock generated on board (oscillator, clock synthesizer, etc.) as the REFCLK input to any GT. INIT_CLK can be driven from a MMCM.

Refer these ARs
http://www.xilinx.com/support/answers/61656.html

http://www.xilinx.com/support/answers/53500.html
https://www.xilinx.com/support/answers/64090.html
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
2,051 Views
Registered: ‎08-01-2008

Re: Can I use MMCM to provide for single-ended GTREFCLK1 Aurora?

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No Xilinx recommends using a clock generated on board (oscillator, clock synthesizer, etc.) as the REFCLK input to any GT. INIT_CLK can be driven from a MMCM.

Refer these ARs
http://www.xilinx.com/support/answers/61656.html

http://www.xilinx.com/support/answers/53500.html
https://www.xilinx.com/support/answers/64090.html
Thanks and Regards
Balkrishan
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1,400 Views
Registered: ‎08-10-2016

Re: Can I use MMCM to provide for single-ended GTREFCLK1 Aurora?

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OK, now that cleared the questions 1. and 2. Thanks @balkris.!

 

However, it is still not clear for me

   >>>>3. How do MGTREFCLK pair pins differ from the internal FPGA clock nets in terms of jitter?

 

I am confused because, I have dealt with 150+ MHz with AXI interfaces in FPGA designs and these clocks were generated by the MMCM. Why is it bad in using MMCM to generate 125MHz for the gt_refclk (which in turn generates a slower 12.5MHz for 0.5Gbps)? Is it hard-wired to some specific hardware in the FPGA? It would be great if anyone could please shed some light on this.!

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Xilinx Employee
Xilinx Employee
1,382 Views
Registered: ‎08-01-2008

Re: Can I use MMCM to provide for single-ended GTREFCLK1 Aurora?

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The quality of the reference clock supplied to the PLL in the 7 SeriesFPGA Transceivers can greatly impact the performance of the transmit jitter and receive jitter tolerance. Jitter or phase noise from the reference clock plays an important role in determining this performance--phase noise being the preferred specification method as it allows the designer to incorporate the various frequency components that a time-based jitter specification might overlook.

 

Depending on the reference clock being used, a different mask needs to be applied. The tables below describe the points of a mask above which the reference clock phase noise should not exceed. If a reference clock does exceed these masks, it results in additional jitter on TX data.

For 7 series GTX and GTH transceivers, the following tables provide the phase noise masks for QPLL and CPLL. For 7 series GTP transceivers,theCPLL table providesthe phase noise mask.

QPLL:

Ref Clock Frequency (MHz)

Phase Noise at Offset Frequency (dBc/Hz)

10 kHz

100 kHz

1 MHz

100.0

-126

-130

-134

125.0

-123

-129

-133

156.25

-122

-127

-132

250.0

-119

-126

-131

312.5

-115

-124

-130

625.0

-110

-116

-120

Note: If your desired reference clock rate is not listed in the table above, please use the phase noise mask for the nearest reference clock frequency.

CPLL:

Ref Clock Frequency (MHz)

Phase Noise at Offset Frequency (dBc/Hz)

10 kHz

100 kHz

1 MHz

100.0

-126

-132

-136

125.0

-123

-131

-135

156.25

-121

-129

-133

250.0

-119

-126

-132

312.5

-116

-124

-131

625.0

-110

-119

-127

Note: If your desired reference clock rate is not listed in the table above, please use the phase noise mask for the nearest reference clock frequency.

Thanks and Regards
Balkrishan
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1,338 Views
Registered: ‎08-10-2016

Re: Can I use MMCM to provide for single-ended GTREFCLK1 Aurora?

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@balkris, thank you once again. This helped a lot.

 

With this information, I could calculate the jitter limitations for MGTREFCLK. Clocking Wizard outputs are not even near this requirement. I checked the CONFIG.CLOCKOUT1_JITTER property of the clocking wizard. It gives a value of 125.247 (ps) for 125MHz output clock. As far as I know, it is the worst case peak-to-peak jitter that the tool estimates. This estimate is based on the MMCM configuration only. In an actual application during runtime, the jitter would be much higher. Am I right? What would a typical real-world value be.? How can I determine that?

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