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kleinkuang
Visitor
Visitor
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Registered: ‎12-03-2017

Cannot set LOC property of ports for Example design of AXI Ethernet Subsystem on VCU118

Vivado: 2017.3

Board: VCU118 Rev2.0

 

I open the example design of AXI Ethernet Subsystem and provide the locations constrants as the following:

捕获.PNG

set_property PACKAGE_PIN AV21 [get_ports sgmii_rxn];
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sgmii_rxn];
set_property PACKAGE_PIN AU21 [get_ports sgmii_rxp];
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sgmii_rxp];
set_property PACKAGE_PIN AV24 [get_ports sgmii_txn];
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sgmii_txn];
set_property PACKAGE_PIN AU24 [get_ports sgmii_txp];
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sgmii_txp];

 

And it seems that these pins cause the following critical warnings:

 

[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance axi_ethernet_0_support/U0_axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_5[1].Gen_5_1.Gen_5_1_1.Nibble_I_RxBitslice_0 on site BITSLICE_RX_TX_X1Y290. The location site type (BITSLICE_RX_TX) and bel type (RX_BITSLICE) do not match the cell type (RX_BITSLICE). Instance axi_ethernet_0_support/U0_axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_5[1].Gen_5_1.Gen_5_1_1.Nibble_I_RxBitslice_0 belongs to a shape with reference instance sgmii_rxp. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["F:/Workspace/FPGA/axi_ethernet_0_ex/imports/axi_ethernet_0_ex_des_loc.xdc":54]

 

Could anyone give me some suggestions?

 

Thanks a lot!

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yenigal
Xilinx Employee
Xilinx Employee
910 Views
Registered: ‎02-06-2013

Hi

 

Make sure the IO placements and Nibble selection match the  board pin location while generating the core as below

 

vcu118_pinloc.png

Regards,

Satish

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