04-28-2016 08:00 AM
Hi,
I am using a Virtex Ultrascale in Vivado 2015.4 and am instantiating a Transceiver Wizard core. At the board level we performed P/N swapping on some of the lanes in order to assist with routing and now I want to change the polarity in the transceiver core. How is this done?
I found in the transceiver documentation (http://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf) that there are two parameters that can be modified (RXPOLARITY and TXPOLARITY) but I am unsure where those should be modified. Should it be in transceiver top level file? In a constraint file? Where the core is being instantiated? Somewhere else?
Thank you,
Jimmy
04-28-2016 08:42 AM
I figured it out.
The RXPOLARITY and TXPOLARITY ports can be added in the transceiver setup under Structural Options. The polarity can then be set in the IP instantiation.
04-28-2016 08:42 AM
I figured it out.
The RXPOLARITY and TXPOLARITY ports can be added in the transceiver setup under Structural Options. The polarity can then be set in the IP instantiation.
04-28-2016 09:30 PM
Are you using loopbacks? If not, don't worry. If you are using loopbacks, you should be aware that the Xilinx transceiver near end loopbacks are applied on the line side of the polarity controls. That means that you will need to change the polarity controls if a near end loopback is active (assuming you want things to work).
Specifically:
set TXPOLARITY to whatever it needs to be to suit your board.
if (near end loopback active)
set RXPOLARITY to the same as TXPOLARITY
else
set RXPOLARITY to whatever it needs to be to suit your board
end
Regards,
Allan