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kef2189
Observer
Observer
4,037 Views
Registered: ‎02-18-2010

Communicating with TI TLK2701

Now that I have managed to get aurora IP working between FPGA boards, I now want to understand how to optimize communication with a non-aurora part.

 

The chief issue that I encountered in dealing with aurora was the necessity of clock correction.  This IP was part of aurora and seems to be baked in the the hard GTP. 

 

How do I handle clock compensation with a non-Xilinx device?

 

I have the channel up and running, but I see the same periodic errors that I was getting when my aurora links were not doing clock compensation correctly.

 

 

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4 Replies
mcgett
Xilinx Employee
Xilinx Employee
4,024 Views
Registered: ‎01-03-2008

Both sides of a serial link must implement the same protocol or the link will not work. Clock correction is just one feature that may be included in a protocol specification.

Since the TLK2701 is an ASSP with a fixed implementation your first place to start is the datasheet for the TLK2701. If it does support clock correction then the next step is to read the RX clock correction section of the MGT user guide to understand how to configure the MGT to match TLK2701.

You will also need to add the same sequence to your transmit logic path so the TLK2701 will be able to clock correct.

If the TLK2701 does not support clock correction then your system will need to use the same clock source for both devices.
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kef2189
Observer
Observer
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Registered: ‎02-18-2010

I read the section you suggested.

 

I think I understand what you are saying.  The TLK2701 doesn't have any explicit clock correction feature - however it does resynchronize when it detects a comma character in the stream.  I don't really know if this is usable for clock correction.  As I see it, I have two options

 

1) Manually send clock correction sequences from the TLK2701 and periodically send commas from GTP. In this case, GTP should work, and I guess we have to hope that the TI chip does the right thing (possible).  

 

2) Figure 7-27 of ug196 says that in a system with Separate Reference Clocks and RX uses RXRECCLK  that no clock correction is needed, but that some latency penalty is incurred.  Is this a worthwhile option?

 

Does anyone have experience with this sort of thing?

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mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

1) This will completely depend on how the TLK2701works

2) If you use the RXRECCLK as the source for the RXUSRCLK reads then there is no need for clock correction sequences.  You will need to figure out some way to bridge between this clock domain and your TX clock domain and account for underflow/overflow conditions.

------Have you tried typing your question into Google? If not you should before posting.
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rcingham
Teacher
Teacher
3,999 Views
Registered: ‎09-09-2010

Perhaps this might help provide a clue or three...
http://e2e.ti.com/support/interface/high_speed_interface/f/138/t/87393.aspx

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"If it don't work in simulation, it won't work on the board."
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