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Registered: ‎11-29-2019

Connecting Ethernet block to PHY on Zedboard

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Hello,

I am currently working with a 7z020clg484-1 Zedboard. I used Vivado to create a block design containing a Zynq7 processing system, a MicroBlaze, and an Axi-Ethernet Subsystem, which is configured to use AVB. I plan to use the AVB module to synchronize an external clock via gPTP. I will, later on, set the RTC via another source for higher precision but that is not done yet. My current goal is to connect the output ports of the Ethernet block with my actual Ethernet port on the Zedboard. I am fairly new to using the Block designer and connecting pins in Vivado. From what I gathered I will need to connect the external pins of my block design to the PHY, which would be the mdio, the rgmii, and the reset pin. I looked into the Zedboard HW user guide but I could not find anything on how to do so. The best thing I could find was the pins of the PHY but I think those are already used by the Processing system. Is what I am trying even possible or is the processing system exclusively using the ethernet port? If not, how would I connect it to my ethernet block? As I said, this is my first time using these tools for this, so I am hopefully just missing something. Thanks in advance.

Sincerely Christian

 

Note: Here is a picture of my ethernet block and what ports I need to connect to the PHY

studentchristian_0-1598351872066.png

I also attached a picture of my whole design so far.

 

 

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Explorer
Explorer
539 Views
Registered: ‎10-05-2010

The PHY on the Zedboard is connected to MIO 16 - 27 and 52 - 53, which connect to the Zynq SOC Ethernet0. That PHY cannot connect to the AXI Ethernet because these MIO pins are not accessible to the PL.

If to do want to use the AXI Ethernet, consider something like the FMC Ethernet card:

http://zedboard.org/product/network-fmc-module

 

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Joe Samson

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3 Replies
Explorer
Explorer
540 Views
Registered: ‎10-05-2010

The PHY on the Zedboard is connected to MIO 16 - 27 and 52 - 53, which connect to the Zynq SOC Ethernet0. That PHY cannot connect to the AXI Ethernet because these MIO pins are not accessible to the PL.

If to do want to use the AXI Ethernet, consider something like the FMC Ethernet card:

http://zedboard.org/product/network-fmc-module

 

---

Joe Samson

View solution in original post

528 Views
Registered: ‎11-29-2019

First of all: Thanks a bunch for the reply!

I was a bit confused by the picture found in the processing systems manual (https://www.xilinx.com/support/documentation/ip_documentation/processing_system7/v5_5/pg082-processing-system7.pdf).

studentchristian_0-1598390568891.png

To me it looks like I can use the EMIO to connect to the MIO. Is that not the case?

Kind regards

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Explorer
Explorer
455 Views
Registered: ‎10-05-2010

The selection of MIO or EMIO is controlled by the peripheral in the PS; there is no primitive in the PL to connect to an EMIO.

If you search the forum you will find this question asked several times, and the answer is always no, the PL cannot connect to MIO pins.

 

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Joe